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Trim clock from pulse-per-second GPS signal?

AKrup
Associate II

Using STM32F030 / F042. I have a GPS receiver onboard which produces a very accurate pulse-per-second signal (~40ns). I want to use this timing source to keep the system clock, or at least the RTC accurate. The user may wander in and out of GPS reception, so the pulses may come at odd intervals, but when they come, their rising edges always align with the top of the second.

I should add that I'm using an 8MHz crystal resonator (HSE).

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I'm doing something a bit more exotic, but if you wanted to mark 1 second ticks with the HSE/PLL you've previously quantified, you could use the ARR setting for the timer to count off your ~32,000,000 ticks to get the integer portion of the error managed, and then modulate that count +/-1 cycle occasionally to account for the accumulating fractional error/bias. This would give you a 31ns saw-tooth, and the ability to read the CNT value to get the fractional second at that resolution.

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Lack of 32-bit TIM, and very crude dividers does make it a bit difficult. I used an L4

Seem to recall the F0 only provides trim for the RTCCLK, you'd need to quantify the HSE and use a combination of HSE/32, the prescalers, and the trim to clock.

Some GPS can generate a persistent frequency which could clock the STM32 in place of a resonator. And most current ones use a TCXO, so even in hold-over a better bet. Others provide an EVENTIN where you could actually time your HSE via a TIM/MCO pulse, likely much more accurately than the STM32 is capable of.

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Thank you, Clive. I'd consider moving up to L4 if it supports my use case. How did you do it on an L4?

> Lack of 32-bit TIM, and very crude dividers does make it a bit difficult.

TIM2 on F042 is a 32-bit counter, if that helps.

I'm doing something a bit more exotic, but if you wanted to mark 1 second ticks with the HSE/PLL you've previously quantified, you could use the ARR setting for the timer to count off your ~32,000,000 ticks to get the integer portion of the error managed, and then modulate that count +/-1 cycle occasionally to account for the accumulating fractional error/bias. This would give you a 31ns saw-tooth, and the ability to read the CNT value to get the fractional second at that resolution.

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Thank you, Clive. I think what you're saying is that 32-bit timers allow smaller sawtooth corrections. I hadn't thought of that. Besides 32-bit timers, does the L4 have anything else that can help the application keep more accurate time?

The granularity is better and I can read/write it atomically. At 32 million cycles I could probably manage the 16-bit prescaler/counter split, but doing a 16/16 split across a pair of timers is not something I want to do.

I'm using an L432 in a small QFN32 package, probably overkill, but it is a proof of concept into a high-margin product, and a chain of internal/external customers who's first question is "but can it do this/that", so I'm giving myself a lot of maneuverability. For something more constrained I'm looking at an L011 part.

Not a big CM0 fan, the CM3/CM4 provides me with a better debugging experience, the SWO/SWV debug output being something permitting all USARTs to function as they would on the end application.

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