the problem about the Ethernet Interrupt, i have debug it two weeks.

aizhixi · ‎2013-05-25

Posted on May 25, 2013 at 17:43

hello:

i do some tests about the ethernet,when i connected the board with PC use the Ethernet crossover cable,the windows remind me the connected have some problems.but i don't know why.

maybe the confiure GPIO have some problems,but i configure it as the same with demo(SMT32F407).I change the GPIO as my board.

the configuration is like this:

/* Configure PA1, PA2 and PA7 */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_0|GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_7;

GPIO_Init(GPIOA, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOA, GPIO_PinSource1, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOA, GPIO_PinSource2, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOA, GPIO_PinSource7, GPIO_AF_ETH);

/* Configure PB8 */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;//GPIO_Pin_5 |

GPIO_Init(GPIOB, &GPIO_InitStructure);

// GPIO_PinAFConfig(GPIOB, GPIO_PinSource5, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOB, GPIO_PinSource8, GPIO_AF_ETH);

/* Configure PC1, PC2, PC3, PC4 and PC5 */

GPIO_InitStructure.GPIO_Pin = GPIO_Pin_1 | GPIO_Pin_2 | GPIO_Pin_3 | GPIO_Pin_4 | GPIO_Pin_5;

GPIO_Init(GPIOC, &GPIO_InitStructure);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource1, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource2, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource3, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource4, GPIO_AF_ETH);

GPIO_PinAFConfig(GPIOC, GPIO_PinSource5, GPIO_AF_ETH);

this is a part of code , i open all the GPIO(connected with PHY ) Alternate Fuction, configure the GPIO like this.

The PYH chip is DP83848C ,The mode of Ethernet i used the MII,I test the RXCLK and TXCLK is 25MHZ, the CLK of PHY is external 25MHZ, I think the CLK configuration have no problem.

at the same time ,i can pass the fuction ETH_MACDMA_Config();

then i judge the the status of PHY,

if (EthInitStatus == 0)

{

LCD_DisplayStringLine(LCD_LINE_8, (uint8_t*)'' Ethernet Init failed '');

while(1);

}

it can pass, that's means the DP83848C have no problem，right?

the DP83848_PHY_ADDRESS 0x01.

Then i initialize the LwIP_Init();

HelloWorld_init();// configure the telnet port 23

while(1)

{

System_Periodic_Handle();

}

the NVIC_Configuration i open the ETH_IRQn;that's all.

when i run tht software ,the LED of Ethernet is on ,that means the hardware is ok, however,the windows reminds the link have some problems,then i ping the IP ,i found can't work.

then i read the Register of PHY ,

RegValue =ETH_ReadPHYRegister(PHYAddress, PHY_BSR)

the value is the 0x0115, is right?(i think it's right)

now , i don't know i can't come into the interrupt，i don't know why ?

can you help me ?thanks。

bouhoula · ‎2013-06-03

Posted on June 03, 2013 at 12:14

The original post was too long to process during our migration. Please click on the provided URL to read the original post. https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006I6cQ&d=%2Fa%2F0X0000000brt%2F9xVsM096ZlTAH160DvrlcSUwb4560fNWa2Tv_n_foJE&asPdf=false

bouhoula · ‎2013-06-03

Posted on June 03, 2013 at 12:19

And this as your eth_bsp.h

(As I can remember I think I found some mistakes in the PHY_MISR and PHY_MICR that had wrong values.)

/**

******************************************************************************

* @file stm32f4x7_eth_bsp.h

* @author MCD Application Team

* @version V1.0.0

* @date 31-October-2011

* @brief Header for stm32f4x7_eth_bsp.c file.

******************************************************************************

* @attention

*

* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS

* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE

* TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY

* DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING

* FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE

* CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.

*

******************************************************************************

*/

/* Define to prevent recursive inclusion -------------------------------------*/

#ifndef __STM32F4x7_ETH_BSP_H

#define __STM32F4x7_ETH_BSP_H

#ifdef __cplusplus

extern ''C'' {

#endif

/* Includes ------------------------------------------------------------------*/

#include ''stm324xg_eval.h''

#include ''stm324xg_eval_lcd.h''

#include ''stm32f4xx_gpio.h''

#include ''stm32f4xx_rcc.h''

#include ''misc.h''

#include ''stm32f4xx_exti.h''

#include ''stm32f4xx_syscfg.h''

/* Exported types ------------------------------------------------------------*/

/* Exported constants --------------------------------------------------------*/

#define DP83848_PHY_ADDRESS 0x01 /* Relative to STM324xG-EVAL Board */

/* Specific defines for EXTI line, used to manage Ethernet link status */

#define ETH_LINK_EXTI_LINE EXTI_Line14

#define ETH_LINK_EXTI_PORT_SOURCE EXTI_PortSourceGPIOB

#define ETH_LINK_EXTI_PIN_SOURCE EXTI_PinSource14

#define ETH_LINK_EXTI_IRQn EXTI15_10_IRQn

/* PB14 */

#define ETH_LINK_PIN GPIO_Pin_14

#define ETH_LINK_GPIO_PORT GPIOB

#define ETH_LINK_GPIO_CLK RCC_AHB1Periph_GPIOB

/* PHY registers */

#define PHY_MICR 0x11 /* MII Interrupt Control Register */

#define PHY_MICR_INT_EN ((uint16_t)0x0002) /* PHY Enable interrupts */

#define PHY_MICR_INT_OE ((uint16_t)0x0001) /* PHY Enable output interrupt events */

#define PHY_MISR 0x12 /* MII Interrupt Status and Misc. Control Register */

#define PHY_MISR_LINK_INT_EN ((uint16_t)0x0020) /* Enable Interrupt on change of link status */

#define PHY_LINK_STATUS ((uint16_t)0x2000) /* PHY link status interrupt mask */

/* Exported macro ------------------------------------------------------------*/

/* Exported functions ------------------------------------------------------- */

void ETH_BSP_Config(void);

uint32_t Eth_Link_PHYITConfig(uint16_t PHYAddress);

void Eth_Link_EXTIConfig(void);

void Eth_Link_ITHandler(uint16_t PHYAddress);

#ifdef __cplusplus

}

#endif

#endif /* __STM32F4x7_ETH_BSP_H */

aizhixi · ‎2013-06-04

Posted on June 05, 2013 at 03:18

thanks for your reply.

i check the file you gave me .

i used the same file. i feel that the problem is not here.

if possiable ,you can send the email me.we can talk about it.

best regard

Roy

aizhixi@gmail.com

aizhixi · ‎2013-06-05

Posted on June 05, 2013 at 09:57

in accordance with the method you said ,i can't receive the packets from the PC, I think the configuration have some problems,however ,you know , i configure the GPIO as Eval board of STM32F407, configure the DMA ,MAC as recommend of ST.

ETH_InitTypeDef ETH_InitStructure;

/* Enable ETHERNET clock */

// ETH_WritePHYRegister(0X01, 0x01, 0x8000);

/* Reset ETHERNET on AHB Bus */

RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_ETH_MAC | RCC_AHB1Periph_ETH_MAC_Tx |

RCC_AHB1Periph_ETH_MAC_Rx, ENABLE);

ETH_DeInit();

/* Software reset */

ETH_SoftwareReset();

/* Wait for software reset */

while (ETH_GetSoftwareResetStatus() == SET);

/* ETHERNET Configuration --------------------------------------------------*/

/* Call ETH_StructInit if you don't like to configure all ETH_InitStructure parameter */

ETH_StructInit(&ETH_InitStructure);

/*------------------------ MAC -----------------------------------*/

ETH_InitStructure.ETH_AutoNegotiation = ETH_AutoNegotiation_Enable;

ETH_InitStructure.ETH_LoopbackMode = ETH_LoopbackMode_Disable;

ETH_InitStructure.ETH_RetryTransmission = ETH_RetryTransmission_Disable;

ETH_InitStructure.ETH_AutomaticPadCRCStrip = ETH_AutomaticPadCRCStrip_Disable;

ETH_InitStructure.ETH_ReceiveAll = ETH_ReceiveAll_Disable;

ETH_InitStructure.ETH_BroadcastFramesReception = ETH_BroadcastFramesReception_Enable;

ETH_InitStructure.ETH_PromiscuousMode = ETH_PromiscuousMode_Disable;

ETH_InitStructure.ETH_MulticastFramesFilter = ETH_MulticastFramesFilter_Perfect;

ETH_InitStructure.ETH_UnicastFramesFilter = ETH_UnicastFramesFilter_Perfect;

/* When we use the Checksum offload feature, we need to enable the Store and Forward mode:

the store and forward guarantee that a whole frame is stored in the FIFO, so the MAC can insert/verify the checksum,

if the checksum is OK the DMA can handle the frame otherwise the frame is dropped */

ETH_InitStructure.ETH_DropTCPIPChecksumErrorFrame = ETH_DropTCPIPChecksumErrorFrame_Enable;

ETH_InitStructure.ETH_ReceiveStoreForward = ETH_ReceiveStoreForward_Enable;

ETH_InitStructure.ETH_TransmitStoreForward = ETH_TransmitStoreForward_Enable;

ETH_InitStructure.ETH_ForwardErrorFrames = ETH_ForwardErrorFrames_Disable;

ETH_InitStructure.ETH_ForwardUndersizedGoodFrames = ETH_ForwardUndersizedGoodFrames_Disable;

ETH_InitStructure.ETH_SecondFrameOperate = ETH_SecondFrameOperate_Enable;

ETH_InitStructure.ETH_AddressAlignedBeats = ETH_AddressAlignedBeats_Enable;

ETH_InitStructure.ETH_FixedBurst = ETH_FixedBurst_Enable;

ETH_InitStructure.ETH_RxDMABurstLength = ETH_RxDMABurstLength_32Beat;

ETH_InitStructure.ETH_TxDMABurstLength = ETH_TxDMABurstLength_32Beat;

ETH_InitStructure.ETH_DMAArbitration = ETH_DMAArbitration_RoundRobin_RxTx_2_1;

EthInitStatus = ETH_Init(&ETH_InitStructure, DP83848_PHY_ADDRESS);

ETH_DMAITConfig(ETH_DMA_IT_NIS | ETH_DMA_IT_R, ENABLE);

after do it, the next step i initilize the LWIP,

in the while() i do it System_Periodic_Handle();

in the file of stm32f4xx_it.c , i check the interrupt. it can't trigger the interrupt.you know.

void ETH_IRQHandler(void)

{

/* Handles all the received frames */

while(ETH_CheckFrameReceived() != 0)

// while(ETH_GetRxPktSize() != 0)

{

LwIP_Pkt_Handle();

}

/* Clear the Eth DMA Rx IT pending bits */

ETH_DMAClearITPendingBit(ETH_DMA_IT_R);

ETH_DMAClearITPendingBit(ETH_DMA_IT_NIS);

}

best regard

Roy

aizhixi@gmail.com

aizhixi · ‎2013-06-05

Posted on June 05, 2013 at 10:03

what the mistakes? what's the value?

aizhixi@gmail.com

Roy

mkbrown32 · ‎2015-07-26

Posted on July 26, 2015 at 20:45

In a STM32F427/DP83848 PCB configuration, I am finding that the LWIP/Ethernet

initialization is hanging at a statement waiting for the Software Reset to clear.

What specifically is the Ethernet MAC engine awaiting ?

I read somewhere that subsequent to issuing the Software Reset,

that the code should then select MII/RMII choice and then

re-enable MAC clocks from the PHY.

This would imply that some sort of Isolate command would be sent

to the PHY prior to Software Reset, and then de-Isolate be issued subsequently.

I do not see that sequence in the example code here, so I interested to know

what has been learned about this initialization hang since these issues were

initially posted.

And specifically, what event(s) signals the MAC to exit Software Reset mode ?

Tesla DeLorean · ‎2015-07-26

Posted on July 26, 2015 at 21:17

In a STM32F427/DP83848 PCB configuration...

Sorry, but that's woefully vague for me, can you support that a bit with a schematic or something?

There are several clocks involved here, and when things seize up in the reset is usually because one of them isn't functioning or behaving as expected at the time in question. There are a lot of interdependencies here created by how you wire things up, and what clock sources and references you use.

Do you have a reset pin attached to the PHY? Do you have the PHY strapped in MII or RMII mode?

This thread is also >2 years old.

Tips, Buy me a coffee, or three.. PayPal Venmo
Up vote any posts that you find helpful, it shows what's working..

mkbrown32 · ‎2015-07-26

Posted on July 26, 2015 at 23:28

I do not have a post-able schematic.

However, I am looking for raw information about what causes a

failure to exit Software Reset of the Ethernet unit in the STM32F427 .

For instance, I am in the process of re-configuring the clocks because the

routing of MCO1 (which is 25MHz) output from the cpu to the X1 pin

of the DP83848 may have been absent.

That may have caused an absence of the corresponding Ethernet MAC clocks (TX, RX and RMII).

What I seek is a statement from ST that this clock absence does cause

(or does Not cause) an STM32F4 Ethernet SR-exit failure.

jones.david · ‎2015-07-27

Posted on July 27, 2015 at 14:24

i had the same problem with rmii dp83848 and i found that there is problem in my schematic so please first check Hardware carefully(pulling up rxd0,rxd1,mdio that is not necessary in rmii).