2016-10-24 06:02 AM
2016-10-24 10:00 AM
> The read/write test of Sram works properly.
What exactly does that mean?
> DMA_InitStructure.DMA_Memory0BaseAddr =(u32)FSMC_IMAGE_ADDRESS; Is this address aligned to word or halfword?> DMA_InitStructure.DMA_MemoryDataSize = DMA_MemoryDataSize_HalfWord;
Try Word here - the FSMC should be able to split word accesses on the AHB side into halfword accesses on its external side.> DMA_InitStructure.DMA_FIFOThreshold = DMA_FIFOThreshold_Full;
Try lower threshold.Is there anything else running on DMA2?
JW