Switching GPIO cause ripple on VDDA. Very strange problem.

[Mikhail Polyakov]

Posted on June 28, 2012 at 16:39

Good day everybody !

I have two strange problems with GPIO  in STM32L151CBU61)  This code I compile  in Keil. Using an oscilloscope I see the time  ports switching.    Why PB7 switches slower than  PA5 PA11 ?        HSI_ON;    SYSTEM_CLOCK_HSI;  RCC->AHBENR |= RCC_AHBENR_GPIOBEN | RCC_AHBENR_GPIOAEN;       GPIOA->MODER &= ~GPIO_MODER_MODER5;    GPIOA->MODER |= GPIO_MODER_MODER5_0;  //PA5 is output    GPIOA->OSPEEDR|= GPIO_OSPEEDER_OSPEEDR5;  // Maximum speed  PA5    GPIOA->MODER &= ~GPIO_MODER_MODER11;    GPIOA->MODER |= GPIO_MODER_MODER11_0;  //PA11 is output    GPIOA->OSPEEDR|= GPIO_OSPEEDER_OSPEEDR11;  // Maximum speed  PA11    GPIOB->MODER &= ~GPIO_MODER_MODER7;    GPIOB->MODER |= GPIO_MODER_MODER7_0;  //PB7 is output    GPIOB->OSPEEDR|= GPIO_OSPEEDER_OSPEEDR7; // Maximum speed  PB7    while(1)    {                GPIOA->BSRRL=GPIO_BSRR_BS_5;  //Hi level on  PA5        GPIOA->BSRRH=GPIO_BSRR_BS_5;  //Low level  PA5        GPIOA->BSRRL=GPIO_BSRR_BS_11;  //Hi level on PA11        GPIOA->BSRRH=GPIO_BSRR_BS_11;  //Low level PA11        GPIOB->BSRRL=GPIO_BSRR_BS_7;   //Hi level on PB7        GPIOB->BSRRH=GPIO_BSRR_BS_7;   //Low level PB7  } 2)But  problem number 1  is  very  important. I do not need fast switch on PB7.   Real trouble is that switching  PA5 causes current consumption pulsation on VDDA !   This pulsation causes changes in the ADC readings. ?apacitors on VDDA do not solve the problem.   In attachment  there is measurement scheme  and  pulsations with amplitude 100mV  when transmitting  one byte through SPI1  , SCK of which  is on PA5. When switching PA11 or PB7 , there is no pulsations on VDDA. Why  PA5  is associated with VDDA  in so strange way ? How to get the correct results from ADC when switching PA5 ?Thank you in advanceMikhail Polyakov,Moskow.A5.   #gpio-vdda-ripple-pulsations

[frankmeyer9]

Posted on June 28, 2012 at 17:01

Is your port PA5 swiching a higher load, or does the port himself source/sink a high current ?

I would add a blocking capacitor at least on VDDA near the uC, and at the load of port PA5, if necessary. Are your Vdd and Vdda coupled somewhere outside the provided schematic ?

[Mikhail Polyakov]

Posted on June 28, 2012 at 18:42

My port PA5 do not swiching a higher load, the pin is 

not connected at all.

I use capacitor onVDDA near uC. 

But

it does not help. 

Even if

there is no

ripple

on the

capacitor and pin VDDA, 

results af ADC

jump

in any case. 

The problem is

that current consumption os VDDA jump, 

internal  

lines  of uC 

have

no-

zero resistance, 

and the ripples

gets to ADC.

VDDA and ADD coupled  outside the provided schematic. 

I tried

to connect VDDA  

differently. 

In  case it connect to VDD 

results of

current measurements are the same.

The problem

is that 

current ripples on VDDA  

cause  voltage ripples on internal  uC lines.

External  

capacitors / coupled / decoupled  do not change the form of ADC 

noise which i get.

The only way to solve the problem is to remove this current consumption ripple.Why this ripple appeared only in case of PA5 switch , and do not appeared in case PA11 PB7 switch ?Maybe there is an internal analog line that connects PA5 and VDDA, 

about which I

do not know, 

and which

can be switch off ?

[emalund]

Posted on June 28, 2012 at 19:16

VDDA and ADD coupled  outside the provided schematic. 

are you saying that you use Vdd as Vref for the A/D, the rest of this post assumes so

External  

capacitors / coupled / decoupled  do not change the form of ADC 

noise which i get.

what's the magnitude of the A/D 'noise'? your eyes and the scope can not see changes below, say ,5% and that will be very visible in the A/D readings. have you tried a RC network from Vdd to Vref? : Vdd - R - Vref -  C - gnd. One aspect all this does not show is ground noise, if you do not have a solid ground plane that will be significant, if you do there will still be some, albeit nominal. do not forget ''a wire is not a wire''. Erik

[frankmeyer9]

Posted on June 28, 2012 at 20:12

Why this ripple appeared only in case of PA5 switch , and do not appeared in case PA11 PB7 switch ?

A ripple occurs when a significant current flows, or more exactly, there is a high di/dt. This, in connection with parasitic inductance of the leads, usually causes that ripple on Vdd. This assumes that the ohmic component of the leads is negligible in this case. The usual remedy in this case is to have low-inductance capacities close to the Vdd pin, buffering the voltage drop with the stored charge. I'm not aware of anything special in regard to PA5. Have you checked that there is not short-circuit to ground ? When you switch PA5, can you measure an equivalent change in the supply current via Vdd ?VDDA and ADD coupled  outside the provided schematic.  Can you be sure that this ripple is not caused by the control characteristics of the Vdd supply ?

I tried

to connect VDDA  

differently. 

In  case it connect to VDD 

results of

current measurements are the same.

I believe this means only GND of Vdd and Vdda are connected. IMHO it would not make sense otherwise.

[Mikhail Polyakov]

Posted on June 29, 2012 at 00:14

Please , look at the picture in attachment.

It can be clearly seen, that rippple on VDDA appeared only when PA5 goes low. In any case, it can not be explained by parasitic capacitances, inductances, and so on... All of these factors are linear, and they would cause same ripples on both fronts of VDDA. I'm talking about the fact that current consumption of VDDA jumps high when switching PA5 from hi to low. And this is due to some internal circuit of uC , no other explanation. Noise in ADC results is 1 last bin in 8bit mode and 4 last bits in 12bit mode. When switching PA5 ADC results goes up , that obviously, as reference voltage VDDA goes low. ________________ Attachments : 444.JPG : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtYi&d=%2Fa%2F0X0000000aRj%2F89IaK0ZUyHtjAQirC1ccBEoRmxo_8J2F.031sKyFHS4&asPdf=false

[frankmeyer9]

Posted on June 29, 2012 at 08:33

Please ,  look at the picture in attachment.

I did, and it does in fact not look like some parasitic effect. I agree with you in this case. And, at least pin-wise, PA5 is not close to Vdda, so a short circuit is not likely. Did you try to measure this ? I would try to observe the current drawn via Vdd while toggling PA5. If only the current on Vdda follows, and not on Vdd, I would contact a ST representative. PA5 has some alternative analogue functions, but when configured as GPIO, I would expect it to load Vdd, and not Vdda.

[Mikhail Polyakov]

Posted on June 29, 2012 at 09:38

I do not

see the point to measure current drop on VDD. It will be there , it mast be there.

I have no short-circuit on PA5. This can be seen 

on the

signal

ostsilogramme on PA5. And 

 in addition , when  I drive PA5 by pull-up / pull-down , form of signal is normal.

VDDA  is a power supply for  HSI, PLL, MSI.  When turn on/of these blocks I measure big current drops on VDDA too. So, 

the only way to save ADC results is to use uC in package where VDDA and VREF pins are different.

But I 

already have this printed board, and drops on VDDA appeard only when switching PA5, where I unlucky have SPI1 SCK , no when switching  PA11  PB7 .

How  to contact ST directly ? I do not see technical support e-mail on there site. 

I was hoping, that their technical specialist will read my post here.

[frankmeyer9]

Posted on June 29, 2012 at 10:59

I do not

see the point to measure current drop on VDD

. My intention was a negative proof, i.e. to show that the current which is switched by PA5 is drawn from Vdda, not Vdd.How  to contact ST directly ? I do not see technical support e-mail on there site. 

I was hoping, that their technical specialist will read my post here.

ST does not necessarily monitor this forum. I would try to contact a sales prepresentative or a distributor. There will be surely some around in moscow. It might be helpful - I know of other problems that did not yet appear in errata sheets, but were acknowledged by ST.

[emalund]

Posted on June 29, 2012 at 14:56

Please ,  look at the picture in attachment.

It can be clearly seen, that rippple on VDDA appeared only  when PA5 goes low.  In  any case, it can not be explained by parasitic capacitances, inductances, and so on...   sure they can '' be explained by parasitic capacitances, inductances, and so on'' the reason for ripple etc is NOT in the schematic (which you do not provide) but in the LAYOUT (which you also do not provide) . My best guess is that you have 'cheated' and made a 2 layer board in which case, what you see is to be expected. anyhow your scope pictures are inconclusive, they should be differential scoping between Vref and ground as well as between the termination of the input and the chip ground,. Erik