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STM32L552CC program counter after bank swapping

dost
Associate II

Hello,

 

I'm using a STM32L552CCT6. For firmware update I want to use the dual flash bank functionality of the controller.

When switching the flash banks with the option bit SWAP_BANK in register FLASH_OPTR what happens to the program counter? Is he also switched to the now second bank to continue the execution of the firmware?

Best regards,

Markus

1 ACCEPTED SOLUTION

Accepted Solutions

The PC isn't changed.

The address decoder into the FLASH array fetches whatever maps to the address you requested 

If the two banks have the same data underneath at the current point of execution you can basically fork()

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View solution in original post

3 REPLIES 3

The PC isn't changed.

The address decoder into the FLASH array fetches whatever maps to the address you requested 

If the two banks have the same data underneath at the current point of execution you can basically fork()

Tips, buy me a coffee, or three.. PayPal Venmo Up vote any posts that you find helpful, it shows what's working..

Thank you for your fast response 👍.

So in my case:
When I run from bank 1, write a updated firmware to bank 2 and make a bank swap then the new firmware on bank 2 is executed immediately from that address to which the program counter is pointing at that moment, isn't it?

 

Best regards,

Markus

FBL
ST Employee

Hello @dost 

 

When switching the flash banks with the option bit SWAP_BANK in register FLASH_OPTR, the address mapping of user flash memory of each bank are swapped. Program counter should be always started executing from bank 1 (0x0800 0000). It is mentioned in Knowledge base article even though the context is different (H7 product).

How to configure swap bank on STM32H7 P2 - STMicroelectronics Community

 

Recommendation to take a look at limitations in errata for example to avoid reading from Bank 2 while writing in it. See ES0448 2.2.10 concurrent read from Bank 2 while erasing it as consequence of decreasing RDP level may result in unpredictable behavior.

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