Hello,
I am working on a simple project at STM32L476 NUCLEO which includes ADC1 + TIM6 + DMA1. No libraries are used.
I am facing the problem where I need to manually set ADSTART bit after each EOS, as it seems it gets cleared and no further conversions are done until bit is set again, even though ADC is running in single mode + hw trigger.
I managed to pinpoint the time when it gets cleared by storing CR register value during various interrupt handlers (EOS, EOC, TIM update). ADSTP is not set from SW side in any case.
No error/outstanding ISR bits are set (EOS & EOSMP).
When is ADSTART initially set?
In ADRDY interrupt handler, I enable timer and set ADSTART.
Details:
SYSCLK is HSI (16MHz), AHB prescaler 1, APB1 prescaler 4, which gives:
ADC1 freq = 4MHz (SYSCLK and CKMODE=01)
TIM6 freq = 4MHz x 2 = 8MHz
TIM6 is basic timer, configured to give update TRGO every 1ms (confirmed using oscilloscope).
ADC1 is configured in single mode (CONT=DISCEN=0), measuring 3 channels (24.5 CC) in Oversampling (N=32, M=32) mode, hw trigger on raising edge, TIM6_TRGO (EXT13).
ADC1->CFGR=0x80000741 --> always
ADC1->CR=0x10000005 --> after ADRDY
ADC1->CR=0x10000001 --> after first EOS
DMA1 is configured in Cycle Mode, half word, 3 transfers.
I can confirm that measurements are correctly sampled and transferred. Also, I can confirm that TIM6 is giving the stable pulse each 1ms. The problem is that I need to engage the software to set ADSTART after each conversion, which I would like to avoid. According to Reference Manual, ADSTART bit should not be cleared by HW in case of hw trigg and single mode. Errata does not mention this issue.
I would be extremely thankful is someone could advise anything here? Have someone faced this issue already? I exhausted internet on this topic and have found nothing useful.
Thanks a lot!
