STM32L431VC - Can VREF+ be sequenced off of VDD/VDDA?

[Shane Kent]

Hello -

I am working on a safety critical application using the STM32L431VC that requires the VREF+ voltage rail to be powered off of a different voltage rail than the main VDD and VDDA rail.

The VDD and VDDA voltage rails are being generated by a single SMPS that is bucking 12V down to 3.3V.

The VREF+ pin of this part is being supplied with a 3.0V rail that is also generated off of the 12V input rail of this design.

Since both the 3.3V VDD/VDDA rail and the 3.0V VREF+ rails are being generated off of the 12V rail independently, there is a chance that the 3.0V rail could be present on VREF+ while 3.3V is sequencing up. (Essentially, 3.0V VREF+ can be present before 3.3V VDD/VDDA).

In order to avoid this, I am planning on sequencing the 3.0V regulator off of the Power Good for the 3.3V regulator. Once 3.3V is steady the power good will allow 3.0V to begin regulation.

The STM32L431VC datasheet is not clear on whether this is OK.

The power sequencing Figure 3 only shows VDD and VDDA.  

Section 6.3.18, Table 66 states that VREF+ should be 2V to VDDA when VDD >= 2V.

 

That doesn't make sense in the case where VREF+ is internally being generated (not externally regulated) by the VREFBUF and before the chip has been programmed to generate a VREFBUF voltage. In that scenario, VREF+ would be 0V until programmed otherwise.

Can anyone provide guidance on whether the sequencing that I described is appropriate for VDD/VDDA and VREF+?

Best,

Shane

[RomainR.]

Hello Shane Kent (Community Member),

And you are right and it's better to secure your sequence orders between VDDA/VDDA and VREF+. At the risk of damaging your device. The reasons is, VREF cannot exceed VDDA.

It may not be clear in the DS, but the following rules should be applied: 

Suppose if VREF voltage is rising before VDDA in Table 6:

For both use case below, the two conditions cannot be met.

• If 0V < VDDA < 2V, VREF must not exceed VDDA.
• If 2V < VDDA < =3.6V, , 2V < VREF < VDDA.

Best regards,

Romain,

[Shane Kent]

Romain -

Thank you for your answer. What is not clear to me is if VDDA is 3.3V and VREF is 0V, will that be a problem? See, for example, our circuit. The VREF is sequenced off of the power supply for VDD/VDDA. There is going to be some amount of time between when PG is released to generate VREF+ after VDD/VDDA is settled at 3.3V.

 

-Shane

[RomainR. · Accepted solution]

Hello Shane Kent,

In STM32G4 RM0440 Rev 7 chapter 6.1 Power supplies.

"VREF+ is the input reference voltage for ADCs and DACs. It is also the output of the internal voltage reference buffer when enabled.

When VDDA < 2 V, VREF+ must be equal to VDDA.

When VDDA ≥ 2 V, VREF+ must be between 2 V and VDDA.

VREF+ can be grounded when ADC and DAC are not active"

Even if VDDA is established before VREF, I suppose ADC or DAC are not active when you apply supply sequence and I don't know timing for Power Good (PG out from buck converter), but in this way it is ok.

Otherwise, if VREF supply rise before VDDA/VDD, you must apply the conditions mentioned.

Best regards,

Romain,

[Shane Kent]

This helps. Thank you, Romain!

-Shane