2017-10-18 10:42 AM
Hi all,
My custom designed bare STM32L052C (QFP48) board refuses to talk to external debuggers (STLinkV2, JLink) when the power goes below 3.0 Volts on Vdd pins.
Only SWD interface and step-down power source are connected. The target voltage is detected correctly by both external debuggers. STLinkV2 is completely new, never connected before. I tried switching debuggers, connecting external PSU, checking all SWD pins, with the same results.
The SWD signals, with the exception of 22 Ohm serial resistors, are pretty much the same as in STM32L073Z-EVAL board, which by the way have been proven to work well down to 1.8 V, using the very same equipment. Reset and SWDIO are normally high when the debugger is connected. BOOT0 is grounded.
I did my best to follow AN4467 'Getting started with STM32L0xx hardware development' during HW design. Since this is an ultra low power application, I omitted 1uF and 4.7 uF blocking capacitors. The board works reliably at 3.3 V. The signal lines are as short as possible, with ground poured between pins and over bottom layer (2-layer PCB). The debug interface is passively connected over TagConnect2030 (RJ12), converted to standard 20-pin JTAG IDC connector over very short ribbon.
No LCD or USB is used in the design. Drop-in replacements are L053C and L063C.
Logic analyzer signal capture failed to reveal anything, since I have no SWD decoder available. The capture files are available at
.Does anyone have an idea what else could be possibly checked?
#stm32l0Solved! Go to Solution.
2017-10-18 06:37 PM
VDDA is used by the POR and PLL/VCO, so needs a connection.
2017-10-18 10:45 AM
Lot of fake/clone ST-LINK V2 pods out there, make sure VTarget is supplied to the pod, and the pod has a buffer chip in it.
2017-10-18 12:50 PM
,
,
https://community.st.com/0D70X000006SqIsSAK
,2017-10-18 02:30 PM
Hi Clive,
Thanks for fast response.
This one was bought from authorized distributor, but I couldn't resist to open it. TI's variant marked NH245 (SN74LVC8T245) in TSSOP-24 is soldered there.
Anyway, JLink has the same circuit and behaves identically with this board.
Is there anything else to try?
EDIT: forgot to mention that JLink is also a genuine one. I would exclude the possibility that these are fake ones.
2017-10-18 02:58 PM
Anything on the board that might threshold the supply and clamp NRST? Check state on NRST pin, check if STM32 POR is kicking in.
2017-10-18 05:41 PM
Thanks for good points forward,
Turvey.Clive.002
There is nothing above SoC's Vdd level, which is sitting on otherwise empty board. NRST circuit is left unpopulated for clarity. I will test NRST BOR level and POR sequence later, since there are some news to be told.
Update: I tried to replace L052C6 with pin compatible L063C8, and it worked at 2.5 V right away. Well, it did once.
Update 2: It looks like VDDA has 100 nF capacitor. However, AVDD-VDD bridging pseudo part is missing on the PCB and schematic, which I didn't notice.
How would L0 behave when VDDA is missing? With VDD at 2.5 Volts, VDDA shows 1.4 Volts from parasitic sources.
Got to go now. Will keep you guys informed tomorrow.
2017-10-18 06:37 PM
VDDA is used by the POR and PLL/VCO, so needs a connection.
2017-10-19 02:08 AM
Got it working. The story follows:
It must have passed through ERC check unnoticed that I forgot to connect AVDD to VDD. When VDD gets right below 3.0 V, then VDDA receives parasitic voltage just below 1.8 V BOR limit. Depending on developer's testing speed, adding 100 nF blocking capacitor to VDDA helps the confusion, as it holds VDDA voltage for just enough time after testing at working voltage to keep BOR off, and make the circuit working for some seconds at lower voltages.
Thanks a lot
Turvey.Clive.002
, I greatly appreciate it!Lubos