STM32H755IIK6 ADC noise

[mosamasa]

I have a custom STM32H755IIK6 board where ADC1 and ADC2 are used as an I/Q receiver. The ADCs are configured in dual regular simultaneous direct mode, 12-bit, at 1.92 MSPS per channel.

The board also includes a LAN8742A Ethernet PHY. The 50 MHz RMII reference clock trace is routed close to the ADC pins (ETH_REF_CLK on P2, ADC inputs on P3 and R3).

Both STM32H755 and LAN8742A use separate 25 MHz crystals.

ADC clock configuration:

• PLL2P = 30.719995 MHz
• DIVM2 = /5
• DIVN2 = x153
• DIVP2 = /25
• FRACN2 = 4915

I observe a periodic spur pattern with peaks at:

• 93.75 kHz
• 280.31 kHz
• 466.88 kHz
• 653.44 kHz
• 840.00 kHz

Noise level is below approximately 14 codes p-p when applying a 0.9 V DC input from a signal generator. I am using an external 1.8 V reference.

The spur frequencies shift when I change the sampling rate, but the amplitudes remain more or less the same.

Initially I suspected the 50 MHz RMII clock because touching the 33 Ω series resistor on ETH_REF_CLK changes the spur waveform, making it resemble a 93.75 kHz square wave. However, increasing the series resistor from 33 Ω to 120 Ω does not significantly affect the noise level.

I do not think VREF is the root cause because I tested both the external reference and the STM32 internal reference, and the results are very similar.

I have not yet tested disabling the LAN8742A completely because Ethernet is currently used for data transfer.

Has anyone seen similar behavior on STM32H7 ADCs, or does anyone have ideas about the root cause?

[EThom.3]

I have a feeling that what you are experiencing is aliasing. That the 50 MHz indeed does disturb the ADC signal. If you change the sampling frequency, the perceived square wave frequency will change as well.

Thought experiment: If the 1.92 MHz sampling rate is correct (Nyquist frequency is then 960 kHz), and the 50 MHz clock is slightly high (just 275 ppm off), then you'll get 50.01375 MHz - (960 kHz × 52) = 93.75 kHz.

If the 50 MHz clock and the sampling frequency are both miraculously spot on, then you would read an 80 kHz square wave on to ADC input. I believe this is too close to be a coincidence.

[EThom.3]

Supplement:

While my calculation of the aliasing frequency was correct, the mathematical expression was misleading. If you want to calculate the aliasing frequency from any clock and sampling frequency, you can use this formula:

fALIAS = fIN - fSAMP × int(fIN / fSAMP + 0,5)

[mosamasa]

Thank you for the explanation and aliasing formula. I performed another experiment which seems to support your theory.

I changed the ADC clock from 30.719995 MHz to exactly 30.6 MHz by disabling FRACN. Since I am using dual ADC direct mode, the effective sampling rate changed from approximately 1.92 MSPS to 1.9125 MSPS.

With the new sampling rate, the spur frequencies shifted to:

• 106.46 kHz

• 288.56 kHz

• 470.65 kHz

• 682.64 kHz

• 864.73 kHz

The spur family still resembles odd harmonics of a square-wave-like disturbance.

The interesting part is that this seems to fit quite well with aliasing from approximately 50.0136 MHz:

• 50.0136 MHz - 26 × 1.9125 MHz ≈ 288.6 kHz

So your explanation appears plausible.

However, I still have difficulty understanding the actual coupling mechanism. My original assumption was direct PCB coupling from the RMII 50 MHz clock trace, but increasing the ETH_REF_CLK series resistor from 33 Ω to 120 Ω did not significantly reduce the spur amplitude.

Because of that, I am now wondering whether the disturbance could originate from internal coupling inside the STM32H755 itself, for example internal bus/DMA activity.

Has anyone seen similar internally-generated alias/spur behavior on STM32H7 ADCs?

[EThom.3]

You are most welcome.

> However, I still have difficulty understanding the actual coupling mechanism. My original assumption was direct PCB coupling from the RMII 50 MHz clock trace, but increasing the ETH_REF_CLK series resistor from 33 Ω to 120 Ω did not significantly reduce the spur amplitude.

> Because of that, I am now wondering whether the disturbance could originate from internal coupling inside the STM32H755 itself, for example internal bus/DMA activity.

From the microcontroller's point of view, it probably doesn't make much of a difference going from 33 Ω to 120 Ω.

Assuming that the input pin capacitance is 5 pF, and ignoring stray capacitance on the board, 120 Ω series resistance will give you a low-pass filter with a cutoff frequency at 265 MHz. A 50 MHz square wave will still pretty much be a square wave after this.

I can only guess what the coupling mechanism is. Both of your suggestions (track-to-track coupling and internal MCU coupling) seem plausible to me. If there was some real current behind this signal, I'd suggest a ground problem, but with 120 Ω in series, I don't believe it can be that. (Does the board have an internal, unbroken ground plane?)

There might be something in the errata sheet about pin-to-pin or peripheral-to-peripheral disturbances.

Apart from this, I don't think I am sufficiently competent to assist you further, and will wish you good luck.