I have a custom STM32H755IIK6 board where ADC1 and ADC2 are used as an I/Q receiver. The ADCs are configured in dual regular simultaneous direct mode, 12-bit, at 1.92 MSPS per channel.
The board also includes a LAN8742A Ethernet PHY. The 50 MHz RMII reference clock trace is routed close to the ADC pins (ETH_REF_CLK on P2, ADC inputs on P3 and R3).
Both STM32H755 and LAN8742A use separate 25 MHz crystals.
ADC clock configuration:
- PLL2P = 30.719995 MHz
- DIVM2 = /5
- DIVN2 = x153
- DIVP2 = /25
- FRACN2 = 4915
I observe a periodic spur pattern with peaks at:
- 93.75 kHz
- 280.31 kHz
- 466.88 kHz
- 653.44 kHz
- 840.00 kHz
Noise level is below approximately 14 codes p-p when applying a 0.9 V DC input from a signal generator. I am using an external 1.8 V reference.
The spur frequencies shift when I change the sampling rate, but the amplitudes remain more or less the same.
Initially I suspected the 50 MHz RMII clock because touching the 33 Ω series resistor on ETH_REF_CLK changes the spur waveform, making it resemble a 93.75 kHz square wave. However, increasing the series resistor from 33 Ω to 120 Ω does not significantly affect the noise level.
I do not think VREF is the root cause because I tested both the external reference and the STM32 internal reference, and the results are very similar.
I have not yet tested disabling the LAN8742A completely because Ethernet is currently used for data transfer.
Has anyone seen similar behavior on STM32H7 ADCs, or does anyone have ideas about the root cause?
