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STM32H753: is there ECC functionnality on L1 cache memories (I+D) ?

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YROSS
Associate II

‎2019-01-24 6:44 AM

 
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waclawek.jan
Guru

‎2019-01-24 8:59 AM

Yes, see Cortex ® -M7 configurations chapter in PM0253.

JW

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waclawek.jan
Guru

‎2019-01-24 8:59 AM

Yes, see Cortex ® -M7 configurations chapter in PM0253.

JW

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