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STM32H7 Dual Core shared memory access

yuri CH


i am currently working with the dual core H7 trying to create some kind of communication systems between the cores. i have read and tried to implement what was suggested in the following thread: Best/easiest way to share data between cores in STM32H745 .

i have created the proper pointer (at address 0x38001000 ) and i protect reads/writes from the same area using the HSem.

My M4 core is periodically writing data to the designated area in the memory while the M7 core is supposed to read this data also periodically.

when i run with debug on the M7 i can see that the M4 is writing the data and the content of memory is constantly changing.

when i also try to read this data, i notice that d the writes by M4 are no longer valid or take effect, data is constant and it is as if something is stuck.

i made sure that the reads/writes are protected by hsem, i also made sure that i am able to read and write by each core to the designated memory address (0x38001000).

current situation does not allow me to send data between the cores.

please advise on how to resolve this issue.


At a guess, perhaps data cache is preventing the M7 from reading the correct data. Disable it while you debug things, and perhaps enable it later with the appropriate cache management.

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yuri CH

Hi, thanks for your anwser.

In did i use D-chache and I-chache as part of the setup needed for utilization of ethernet comms.

i have tried your suggestion and it seems to work, when D-chache is disabled i can read the data properly.

on the other hand, it disruppts the correct work of ethernet comms.

Could you please explain why this solves it?

my defenitions of the MPU and cache:

as i understand it we are talking about completly different parts of the memmory.



In short, the cpu keeps track of data locally and assumes it isn't modified externally (by another core or by DMA) in order to speed up execution.

There are many more detailed explanations on how cache works online. Here is one:

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yuri CH

perhaps i didnt explain my self properly... 🙂

i know what is cache memory, i am looking for information on how to allow the enablment

of D-chache and my inter core data exchange co exist...

perhaps some kind of cache managment as you said before? where can i find information on that?

Cache management can be done by the clean and invalidate functions which are covered in the linked document.
The linked document also gives 4 different solutions for how to manage cache.
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