Hello,
the reference manual of the STM32G4 Series states, concerning the arbitration of mem2mem transfers:
When a channel x is programmed for a block transfer in memory-to-memory mode,
re arbitration is considered between each single DMA transfer of this channel x. Whenever
there is another concurrent active requested channel, the DMA arbiter automatically
alternates and grants the other highest-priority requested channel, which may be of lower
priority than the memory-to-memory channel.
I find this paragraph a bit hard to understand.
Lets say I configure two MEM2MEM transfers on different channels (say Channel 1 and Channel 2) on the same DMA instance (say DMA1) with a certain length (say 1000 words with 32 bit each) and with different priorities set (say Channel 1 low, Channel 2 high) and all interrupts (HT, TC, TE) enabled. If I now enable both channels directly after each other, starting with the low priority one (Channel 1 in this case), I'd expect the following order of interrupts:
- Channel 2 HT
- Channel 2 TC
- Channel 1 HT
- Channel 1 TC
In short, I'd expect the high priority channel to "overtake" the low priority channel and finish all 1000 transfers before the low priority channel would continue where it left.
The order of interrupts I get in my implementation:
- Channel 1 HT
- Channel 2 HT
- Channel 1 TC
- Channel 2 TC
So it seems the transfers run more or less in parallel, with the channel that was started first "in the lead". The priority does not seem to make a difference here.
When I say priority, I do talk about DMA channel priority here, not DMA channel interrupt priority.
Is what I observed intended behaviour and I missunderstood the reference manual, or should I look at my implementation again?
Thanks for your help!
