Is the ADC available in low power run and sleep mode for the STM32G070RB?
I am trying to monitor 4 ADC channels continuously with a power budget of under 100uA. I would use the analog watchdog to wake the processor in the event of tripping the high or low threshold. I have a possible solution using a standalone ADC, but I thought it was worth exploring the processor.
I have got the power down to roughly the right level ~100uA using low power mode and the LSI as main clock, however I noticed a line in the reference manual that says the ADC will not run in low power mode. Page 262 / 263 of the reference manual states
"The internal ADC voltage regulator internally uses an analog reference delivered by the power control unit through a buffer. This buffer is always enabled when the main voltage regulator of the power control unit operates in normal Run mode (refer to Reset and clock control and power control sections). If the Main voltage regulator enters low-power mode (such as Low-power run mode), this buffer is disabled and the ADC cannot be used."
However in this power control pdf
https://www.st.com/resource/en/product_training/STM32G0-System-Power-control-PWR.pdf
It shows the ADC is available in G0 devices in low power run and sleeps modes in the text as well as the summary on page 31.
I'm guessing the reference manual for this specific device is correct, but I thought it was worth confirming.
Thanks for your help.
