STM32F767 ART versus ICache

[John F.]

Posted on May 08, 2018 at 15:37

I'm using an STM32F767 at 216 MHz with LL_FLASH_LATENCY_7. The IDE is Keil with IROM (Flash) at 0x8000000. STM documentation AN4667 says, 'Flash memory is accessible by the CPU through ITCM starting from the address 0x00200000' and 'Flash memory is accessible by the CPU through AXI starting from the address 0x08000000'. Reviewing the Flash memory interface paths it's clear that the flash is accessed via AXI/AHB. The advice is 'the instruction or/and data caches should be enabled in this configuration to get 0-wait-state-like access to the Flash'.

I have added the line, 'SCB_EnableICache();' to my SystemClock_Config function in file main.c.

Is that correct, sufficient and complete? I do not currently wish to cache data memory. I just want the same instruction fetch / execution performance increase I would have got from the ART accelerator in an STM32F4 for example.

I've searched the forum and STM documents and am now overwhelmed with information and seeking clarity.

thanks, John F.

#stm32f7-icache-art

[Nesrine M_O]

Posted on May 08, 2018 at 16:32

Hi

FitzGerald.John

Please have a look to this thread

https://community.st.com/0D50X00009Xkf60SAB

-Nesrine-

[John F.]

Posted on May 08, 2018 at 16:57

Hi Nesrine. Thanks for the link. Anyone else comments please?

[John F.]

Posted on May 09, 2018 at 09:17

I thought Clive One or Jan Waclawek might have responded to this.

Here's an example of information that I find confusing:

The CMSIS documentation says,

'Before enabling the instruction cache, you must invalidate (

http://www.keil.com/pack/doc/CMSIS/Core/html/group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3

) the entire instruction cache if external memory might have changed since the cache was disabled.'

OK that makes sense ... but the Flash content won't have changed in my system ... but then it also says :

'After reset, you must invalidate (

http://www.keil.com/pack/doc/CMSIS/Core/html/group__Icache__functions__m7.html#ga50d373a785edd782c5de5a3b55e30ff3

) each cache before enabling it.' which I can do but don't understand the need as I'd have thought the whole point of reset was ... to reset everything.

Edit : In fact the CMSIS  __STATIC_INLINE void SCB_EnableICache (void) function invalidates the cache before enabling it.

__STATIC_INLINE void SCB_EnableICache (void)

{  #if (__ICACHE_PRESENT == 1U)    __DSB();    __ISB();    SCB->ICIALLU = 0UL;                     /* invalidate I-Cache */    SCB->CCR |=  (uint32_t)SCB_CCR_IC_Msk;  /* enable I-Cache */    __DSB();    __ISB();  #endif}

[AvaTar]

Posted on May 09, 2018 at 10:08

'After reset, you must invalidate (

/external-link.jspa?url=http%3A%2F%2Fwww.keil.com%2Fpack%2Fdoc%2FCMSIS%2FCore%2Fhtml%2Fgroup__Icache__functions__m7.html%23ga50d373a785edd782c5de5a3b55e30ff3

) each cache before enabling it.' which I can do but don't understand the need as I'd have thought the whole point of reset was ... to reset everything.

Which is not necessarily the same.

The cache will not have default values after a reset, unlike the config registers.

I'm currently dealing with a similar issue on a proprietary japanese MCU. Before enabling ICache, I need trigger an invalidate/clear bit in a config register.