Posted on January 27, 2017 at 17:12 My board is not based on Discovery schematics, I'm free to choose any possible combination of IOs and PF6,7,8,9 looks pretty good. So if you say its okay, I'll fix this pinout in my design.
And yes, this
/external-link.jspa?url=http%3A%2F%2Fwww.st.com%2Fcontent%2Fccc%2Fresource%2Ftechnical%2Fdocument%2Fapplication_note%2Fgroup0%2Fb0%2F7e%2F46%2Fa8%2F5e%2Fc1%2F48%2F01%2FDM00227538%2Ffiles%2FDM002275pdf%2Fjcr%3Acontent%2Ftranslations%2Fen.DM002275pdf
is exactly what I'm reading.Quote follows:
The IO2 and IO3 lines are optional and can be used for other purposes such as:
•
When used (IO2 and IO3 are connected to the QSPI memory): IO2 and IO3 pins
should be configured as for IO0 and IO1. To allow communication with memory device:
–
IO2 is in output mode and forced to ‘0’ to deactivate the “write protect�? function – IO3 is in output mode and forced to ‘1’ to deactivate the “hold�? function
– This is managed by the hardware (Quad-SPI peripheral) during all communication
phases
•
When not used, the nWP and nHOLD memory device pins have to be connected
respectively to VDD and VSS while IO2 and IO3 pins could be used for other purposes.
But when I'm reading datasheet for SPI flash (
SST25VF032B
for instance), I see this:
The Write Protect (WP#) pin enables the lock-down function of the BPL bit (bit 7) in the status register.
When WP# is driven low, the execution of the Write-Status-Register (WRSR) instruction is determined
by the value of the BPL bit (see Table 2).
When WP# is high, the lock-down function of the BPL bit is disabled.
I've checked few different chips from different vendors. Logic behind #WP is the same everywhere, and this is exactly what is confusing me: hardware in STM32 forcing this pin to '0' assuming that this will disable WriteProtect function, but in fact result is opposite and all writes to Status Register are blocked unless SR.BPL bit was previously cleared. Fortunately enough, in SST25 this bit (SR.BPL) is cleared on power up.
I guess, in case if legacy SPI flash is used, QSPI.IO2 pin should be configured as GPIO and forced to '1' or '0' when its really needed.
