Posted on July 14, 2016 at 14:51I have a Spartan-6 FPGA connected to an STM32F746IG using the FMC. The FMC is configured for SRAM in region 1.1 (0x60000000). I have disabled caching of the FMC region in the MPU. I see FMC read & write cycles with the proper timing. Pull-ups are enabled on D[15:0].
When I do several back-to-back writes, the cycles look normal until the final write. On the last write, the data bus continues to be driven by the FMC for 450-500 nsec. I would expect to see the data lines pull high very soon after NE1 goes high.
I ran the same code on an F7 eval board with nothing connected to the FMC and I see the same behavior on write cycles.
I don't see any FMC SRAM issues in the errata. The FMC registers don't seem to have anything related to a bus hold feature. Does anybody have any suggestions?
regards,
Kurt
