stm32F4Discovery audio codec problem

Posted on July 20, 2012 at 18:19

Anyone? Is something that I've posted unclear or just no one knows?

 

No it's just uninformative. You've tried to port some example code into some other construct that looks like FreeRTOS, you've missed some critical steps, not really provided a complete context or code, and posted a code fragment which doesn't illustrate why it might have failed. You're basically asking people to guess what steps you missed in this process. Missing one is probably sufficient to break the whole.

Perhaps there are other code dependencies, like interrupts, clocks, timers, SysTick, DMA, etc which are handled differently or not at all by FreeRTOS.

Posted on July 23, 2012 at 14:07

I've commented #include freertos.h ans tasks.h. It's just simple infinite loop in main function. And it is still doesn't work.

int main(void)

{

HardwareInit();

/*

xTaskCreate( vTaskLED1, ( signed char * ) ''LED1'', configMINIMAL_STACK_SIZE, NULL, 2,

                       ( xTaskHandle * ) NULL);

                       */

/* xTaskCreate( vTaskLED2, ( signed char * ) ''LED2'', configMINIMAL_STACK_SIZE, NULL, 2,

                       ( xTaskHandle * ) NULL);

// GPIO_SetBits(GPIOD, GPIO_Pin_12 | GPIO_Pin_13);*/

EVAL_AUDIO_Play((uint16_t*)((uint16_t*) (&AUDIO_SAMPLE+58)),  990000-58);

// vTaskStartScheduler();

for (;;);

}

So it's just initialization of codec which returning '0' to me (which I can see by green led lightning) and then

EVAL_AUDIO_Play((uint16_t*)((uint16_t*) (&AUDIO_SAMPLE+58)),  990000-58); 

which doesn't work for some reasons.

and infinite loop after it.

Posted on December 07, 2012 at 14:09

Hi Michael,

Did you ever get this FreeRTOS integration to work? I am wrestling the exact same phenomenon since a couple of hours myself.. =)

Edit: system_stm32f4xx.c turned out to be the culprit.

Posted on May 13, 2014 at 12:09

Anyone could give me pointers on what was wrong with your code ?

I'm struggling with the same problem, 

everything seems fine, but no sound output at all ..

thanks!

Posted on May 13, 2014 at 13:48

So today's clues are codec and system_stm32f4xx.c

Perhaps the I2S PLL is not set up correctly?

Posted on May 13, 2014 at 22:01

This is the codec & PLL config i'm using

for a 48Khz playback, which looks exactly

like the config used in the example :

/*------------------------------------

CONFIGURATION: Audio Codec Driver Configuration parameters

----------------------------------------*/

/* Audio Transfer mode (I2S Interrupt) */

//#define I2S_INTERRUPT

/* Audio Transfer mode (DMA, Interrupt or Polling) */

//#define AUDIO_MAL_MODE_NORMAL

#define AUDIO_MAL_MODE_CIRCULAR

/* For the DMA modes select the interrupt that will be used */

#define AUDIO_MAL_DMA_IT_TC_EN

//#define AUDIO_MAL_DMA_IT_HT_EN

//#define AUDIO_MAL_DMA_IT_TE_EN

/* Select the interrupt preemption priority and subpriority for the DMA interrupt */

#define EVAL_AUDIO_IRQ_PREPRIO           0

#define EVAL_AUDIO_IRQ_SUBRIO            0

/* Uncomment the following line to use the default Codec_TIMEOUT_UserCallback()

   function implemented in stm32f4_discovery_audio_codec.c file.

   Codec_TIMEOUT_UserCallback() function is called whenever a timeout condition

   occurs during communication (waiting on an event that doesn't occur, bus

   errors, busy devices ...). */

//#define USE_DEFAULT_TIMEOUT_CALLBACK

/* Enable this define to use the I2S DMA for writing into DAC register */

//#define DAC_USE_I2S_DMA

/*----------------------------------------------------------------------------*/

/************************* PLL Parameters *************************************/

/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */

#define PLL_M      25

#define PLL_N      336

/* SYSCLK = PLL_VCO / PLL_P */

#define PLL_P      2

/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */

#define PLL_Q      7

#define PLLI2S_N   258

#define PLLI2S_R   3

Posted on May 13, 2014 at 22:13

Found it ...

I was missing the actual I2S clock setup in system_stm32f4xx.c :

  /******************************************************************************/

/*                          I2S clock configuration                                                                          */

/******************************************************************************/

/* PLLI2S clock used as I2S clock source */

RCC->CFGR &= ~RCC_CFGR_I2SSRC;

/* Configure PLLI2S */

RCC->PLLI2SCFGR = (PLLI2S_N << 6) | (PLLI2S_R << 28);

/* Enable PLLI2S */

RCC->CR |= ((uint32_t)RCC_CR_PLLI2SON);

/* Wait till PLLI2S is ready */

while((RCC->CR & RCC_CR_PLLI2SRDY) == 0)

{

}