STM32F439 and external core supply: NOT WORKING!

[our]

Posted on December 09, 2014 at 20:10 BYPASS_REG = High, VCAP = 1.2V (supplied externally), VCC = 1.8...3VResult: NRST

is

driven low

constantly

by the MCU, nothing works. The same board works OK when BYPASS_REG = Low and the core's external supply disconnected. Possible reasons? And please report if anybody

successfully

uses external core supply!

[Tesla DeLorean]

Posted on December 09, 2014 at 20:38

Do you have VSSA/VDDA connected to a supply? The Power-On-Reset (POR) circuit is on the analogue supply.

[our]

Posted on December 09, 2014 at 20:45

Yes, at least this is present on the schematic. I

n addition

, DAC works OK, and POR actually works OK when BYPASS_REG = low, I

clearly

see its threshold of about 1.7V. UPD:: All two my boards show this effect.

[waclawek.jan]

Posted on December 09, 2014 at 21:12

I don't use external V12 source, but do you have the external V12 supervisor connected to PA0, as described in chapter 3.18.2 ''Regulator OFF'' of STM32F437/439 datasheet rev.5?

JW

[our]

Posted on December 09, 2014 at 21:21

In my case, PA0 is connected to NRST and further both they go to the external supervisor, which is now desoldered because I had to figure out who drives NRST down (pullup present).

It appeared to be the MCU itself.

[waclawek.jan]

Posted on December 09, 2014 at 22:04

> In my case, PA0 is connected to NRST and further both they go to the external supervisor,

> which is now desoldered because I had to figure out who drives NRST down (pullup present).

> It appeared to be the MCU itself.

Disconnect them, and connect PA0 to the external supervisor, and leave NRST unconnected. What is the trip level of the external supervisor? It should be between the actual value of V12 and V12min (1.10V for 120MHz, see values for V12 in table17) so that it releases PA0 when V12 is up. The margin appears to be very narrow indeed. Where is PDR_ON connected? I assume it is connected to VDD, as you reported NRST to be active below 1.7V. JW

[our]

Posted on December 09, 2014 at 22:26

>>> Disconnect them, and connect PA0 to the external supervisor

It is hard, and I believe it should not help. From the two pictures on p.29 (STM32F439xx datasheet Rev.5) we can see that PA0 and NRST can be released on the same time, otherwise PA0 should be released LATER then NRST.