STM32F429 timer debug question

[baev_al]

Posted on September 14, 2014 at 20:03

Hello friends.

I use EWARM as IDE.

The platform is STM32F429I-DISCO

Now I study timers' behavior. When I use one step through the code while debugging (Step Into in the EWARM) the value of the CNT register changes as it likes. After each step I see absolutely non-related values. Is this because the CLK doesn't stop and the timer continues to increase while the marker is stopped at certain instruction? How can I debug properly?

Here is how I initiate the timer:

RCC_APB1PeriphClockCmd(RCC_APB1Periph_TIM3, ENABLE);

TIM_TimeBaseInitTypeDef timerInitStructure;

timerInitStructure.TIM_Prescaler = 1000;

timerInitStructure.TIM_CounterMode = TIM_CounterMode_Up;

timerInitStructure.TIM_Period = 0xffff;

timerInitStructure.TIM_ClockDivision = TIM_CKD_DIV1;

timerInitStructure.TIM_RepetitionCounter = 0;

TIM_TimeBaseInit(TIM3, &timerInitStructure);

TIM_ITConfig(TIM3, TIM_IT_Update, ENABLE);

TIM_Cmd(TIM3, ENABLE);

[chen]

Posted on September 15, 2014 at 15:13

Hi

''When I use one step through the code while debugging (Step Into in the EWARM) the value of the CNT register changes as it likes. After each step I see absolutely non-related values. Is this because the CLK doesn't stop and the timer continues to increase while the marker is stopped at certain instruction?'' Yes, correct. The Timer's count register is increased at the rate you configured it to regardless of what you are doing with the debugger. ''How can I debug properly?'' Well, you are asking - how can I debug the hardware? I hope that ST have done that for you! What you are really asking is : How do I know if I have configured the timer correctly? or How do I configure the timer to ..... To answer question about have I configured it correctly : try enabling trigger event on count match enabling the interrupt on trigger event count match in the ISR, toggle an IO pin Now, you can measure the freq of the toggle on the IO pin and see if it matches what you think it should be.

[Tesla DeLorean]

Posted on September 15, 2014 at 16:38

The debugging thing confused me too, what exactly are you trying to debug, the timer either ticks properly or it doesn't, and a scope is the best tool.

Remember the Prescaler and Period values are N-1, so divide the source clock by 1000, you need 999 You can use DBGMCU to stop assorted timers when the processor is stopped.

/**
* @brief Configures APB1 peripheral behavior when the MCU is in Debug mode.
* @param DBGMCU_Periph: specifies the APB1 peripheral.
* This parameter can be any combination of the following values:
* @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted
* @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted
* @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
* @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted
* @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted
* @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
* @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted
* @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted
* @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted
* @arg DBGMCU_RTC_STOP: RTC Wakeup counter stopped when Core is halted.
* @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
* @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted
* @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
* @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted
* @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted
* This parameter can be: ENABLE or DISABLE.
* @retval None
*/
void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
{
/* Check the parameters */
assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
assert_param(IS_FUNCTIONAL_STATE(NewState));
if (NewState != DISABLE)
{
DBGMCU->APB1FZ |= DBGMCU_Periph;
}
else
{
DBGMCU->APB1FZ &= ~DBGMCU_Periph;
}
}

[baev_al]

Posted on September 15, 2014 at 17:14

''To answer question about have I configured it correctly : try enabling trigger event on count match

enabling the interrupt on trigger event count match in the ISR, toggle an IO pin'' This (interruption) exactly was a problem :). So I tried to see what flags would be set during overflow.

[chen]

Posted on September 15, 2014 at 18:02

Hi

''This (interruption) exactly was a problem :). So I tried to see what flags would be set during overflow.'' So what was the problem you were having? You should be able to stop in the ISR and examine the TIMx-SR register without any problems. I think the status bits stay set until you clear them. That is definitely true for the Count Match event status bit. The ISR must clear this status bit in order for the thing to work correctly.