I connect STM32F429 with an eMMC NAND via SDIO interface(CLK CMD & DAT0).
This initialization sequence for eMMC should be CMD0, CMD1(wait OCR bit31), CMD2, CMD3, CMD9, .....
The eMMC driver is tested ok on STM32F103 system, including init, read, write, erase operation.
And I transplant it to STM32F429, after CMD3 is well responsed, the CMD or DATA CRC error happends with high probability.
CMD1 & CMD2 always response right OCR&CID and never return CRC error.
Which means after CMD3, the eMMC device change its CMD line from OpenDrain mode to PushPull mode.
For PushPull mode pins(cmd or data pins), the data error rate is very high.
e.g. 0xD0270132(expecte data) is reconized as 0xD0270134, 0xA04E0268, 0xD04E0264, ... sth. like this
A slow climbing curve can be founded on CMD pin using oscilloscope in this situation.
How can explain this situation, and what's the probable cause?
The circuit for SDIO connection keeps the same as STM32F429 (direct connection with 10k pullup resister on CMD and DATA0), and the pipheral configuration for GPIO and SDIO are almost the same, speed is under 400k.
