STM32F427 adding SDRAM with NOR Flash and SSD1963 to FMC
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‎2013-10-09 1:19 AM
Dear All,
If I use the FMC external bus to drive SDRAM and also some NOR flash and a display via an SSD1963, do you recommend buffering the bus between the SDRAM and the Flash / Display? I've looked at various application notes for other CPUs, and also the schematics of the new Eval boards, and they seem to contradict each other. A note on the schematic for the STM324x9I-EVAL board asks for the SDRAM signals (Data / Address / Control) to be the same length, and has no buffer. Not sure at what length of trace, this becomes critical for the SDRAM. An application note from ST might help, if one exists? Thanks. #sdram-fmc-stm32f427-stm32f429- Labels:
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FMC-FSMC
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‎2013-10-10 12:07 AM
If the display (controller) is at the end of a cable or flexi circuit, I'd buffer the signals to that and keep the interconnections between the buffer (microcontroller side), microcontroller and memories short and well controlled. Maybe use (~ 100R) ''Series Termination'' resistors in the drive to the cable or flexi circuit on the buffer (display side).
For a practical guide to signal integrity in a similar application, have a look at,http://www.freescale.com/files/32bit/doc/app_note/AN2536.pdf
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‎2013-10-10 1:06 AM
Thanks John,
That was the conclusion I was coming to, I found these 2 docs also:-http://www.analog.com/static/imported-files/tutorials/MT-097.pdf
Do you think buffering between the SDRAM and Flash is over the top? Cheers.- Mark as New
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‎2013-10-10 4:10 AM
I'd be guided by other designs. Unless you need to place the SDRAM and Flash a long distance apart, I wouldn't buffer between them. Remember that buffering adds propagation delay and introduces additional tracking. Keep the fast digital components together and buffer the slower Display signals which probably also use longer traces.
(thanks for the other links.)