STM32F417: SPI via DMA

[tomwinkler9]

Posted on November 30, 2012 at 16:02

Dear STM324 Developers,

I'm working on a custom board based on the STM32F417 mcu.  I want to connect my board to an other system via SPI2. This other system will act as SPI master (slave mode is not supported on this device) while the STM is slave. I'm so far only interested in data that is transmitted from the STM to the master and I'm ignoring all data coming in from the master. I got the setup working based on SPI interrupts. The SPI clock (400kHz) is driven by the master. My code for SPI interrupt based transfer of 16 bytes can be found in pastebin: [[this link/image has been flagged as malicious by our security scan software and has been deleted]] In the next step I wanted to add DMA but so far was unable to get it running. My extended code which uses DMA for data reception can be found in pastebin:

[[this link/image has been flagged as malicious by our security scan software and has been deleted]]

Upon startup of the board I get a DMA interrupt DMA_FLAG_TEIF4 (transfer error). The interrupt is cleared by my code. The next thing I get is another interrupt: DMA_FLAG_FEIF4 (fifo error). After that the board is still alive (LED is toogled in the loop at the end of spi test function) but when I try to transfer data via SPI (i.e., master generates clock) nothing happens. I think that DMA is disabled due to the transfer/fifo error. My understanding is that the DMA initially tries to fill the fifo. That's why I'm seeing DMA interrupts upon boot even though there is no active SPI clock at this point. However, filling the fifo seems to fail. As an alternative I also tried ''direct mode'' (fifo disabled) but interestingly got the same result (transfer error followed by fifo error). When I check the fill state of the fifo when getting the interrupts then the fifo state is reported as empty. And one more observation: I also tried to reduce the DMA buffer size from 16 to 1 element. In this case I get one successful transfer (DMA_FLAG_TCIF4 = transfer complete) followed again by a DMA_FLAG_TEIF4 (transfer error) and a DMA_FLAG_FEIF4 (fifo error). In the DMA_FLAG_TCIF4 handler I reset the DMA buffer size and I also reset the memory base address. All in all: I spent the past three days on getting the DMA for SPI2 working but so far without luck. I'd be happy if someone could point out what I might be doing wrong. Thank you, Thomas

[Tesla DeLorean]

Posted on November 30, 2012 at 16:30

Need the ampersand so you get an address, not content of register at initialization

DMA_InitStructure.

DMA_PeripheralBaseAddr

=

(uint32_t)&SPI2

->

DR

;

[tomwinkler9]

Posted on November 30, 2012 at 21:58

Hi Clive,

I can't believe that I overlooked this stupied mistake... You made my day - thank you very much! It is working nicely now.There is one more thing that is unclear to me. In this sutiation where the DMA is going from memory to peripheral - what is a good fifo threshold level? Right now I'm using DMA_FIFOThreshold_HalfFull. My thought is that I want to avoid underruns. I guess DMA_FIFOThreshold_1QuarterFull would be better since the DMA would have to kick in less frequently?When doing DMA in the opposite direction (periph to mem) I usually use DMA_FIFOThreshold_Full. In the mem to periph case the equivalent setting would be ''Empty'' but it seems that no such option exists. What is the reason for that?Thank you,Thomas

[Tesla DeLorean]

Posted on November 30, 2012 at 22:54

No problem, your eloquent description of the problem lead me right to it. Sometimes it just helps to explain what you're doing and let someone else scan the code, we can all be blind to things in plain sight. And I'm pretty good at static code analysis.

Anyway it looked like a problem that would be bugging you all weekend, and I know I've had those Friday's before. I haven't really done much analysis, or put much thought into the DMA FIFO, I suspect it only becomes critical when the bus gets very highly contended, or the data is particularly bursty. This would scare me as others have identified DMA errata when too many channels are active. I don't think I've seen a diagram with enough detail to get beyond general assumptions about how it might work. Have a good weekend. -Clive