STM32F407VGT6 and I2S

Posted on July 16, 2012 at 18:06

Hi all!!!

Please help me. A have problem with I2S interface in this MC. I need to work with audio codec cs4221 by means of I2S. I setup I2S2 interface in full-duplex mode (I2S2- Master reciev, I2S2ext - Slave TX). Data lenghth - 24 bit, chanel length - 32 bit. The problem it is that sometimes (every jne of three) i recieve frame with value 0xfffe or something like this. I do not understand, what is the problem? And I use tme I2S_MCK (256*22050=5644800Hz) for CS4221, Fs=22050Hz.And Another - why I2S_MCK presents on PC6 (pin 63 in LQFP100) only when I2S is Master-recieve, not Master-TX? About this says nothing in datasheet.

my source code:

void I2S_init (void)

{

  /*Ã�àñòðîéêà I2S

  ÷àñòîòà äèñêðåòèçàöèè 22050Ãö

  f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN / PLLM)

  f(PLL I2S clock output) = f(VCO clock) / PLLI2SR

  */

RCC->AHB1ENR|=RCC_AHB1ENR_GPIOCEN;//âêëþ÷èë GPIOC 

GPIOC->MODER|=GPIO_MODER_MODER6_1;//âûõîä AF

GPIOC->OSPEEDR=0;

GPIOC->OSPEEDR|=0x1000;

GPIOC->AFR[0]|=0x05000000;//AF5-MCKI2S

RCC->AHB1ENR|=RCC_AHB1ENR_GPIOBEN;//âêëþ÷èë GPIOB

GPIOB->MODER|=GPIO_MODER_MODER12_1;//âûõîä AF

GPIOB->MODER|=GPIO_MODER_MODER13_1;//âûõîä AF

GPIOB->MODER|=GPIO_MODER_MODER14_1;//âûõîä AF

GPIOB->MODER|=GPIO_MODER_MODER15_1;//âûõîä AF

GPIOB->OSPEEDR=0;

GPIOB->OSPEEDR|=0x55000000;

GPIOB->AFR[1]|=0x56550000;//AF5-I2S/SPI

RCC->PLLI2SCFGR=0;//îáíóëÿþ

RCC->PLLI2SCFGR|=PLLI2SN(429);//

RCC->PLLI2SCFGR|=PLLI2SR(4);//

RCC->CR|=RCC_CR_PLLI2SON;//Âêëþ÷èë PLL  I2S

#ifndef SIMULATOR

while ((RCC->CR&RCC_CR_PLLI2SRDY)!=RCC_CR_PLLI2SRDY);//ïîêà çàðàáîòàåò PLL

#endif

RCC->APB1ENR|=RCC_APB1ENR_SPI2EN;//âêëþ÷èë Spi2

SPI2->I2SCFGR|=SPI_I2SCFGR_I2SMOD;//âêëþ÷èë I2S

SPI2->I2SCFGR|=SPI_I2SCFGR_DATLEN_0;//24áèò äàííûå

SPI2->I2SCFGR|=SPI_I2SCFGR_CHLEN;//32áèò äëèíà äàííûõ 

SPI2->I2SPR=I2SDIV(9);//

SPI2->I2SPR|=I2SODD(1);//

SPI2->I2SCFGR|=I2SCFG(3);//�åæèì Ìàñòåð - ïðèìåíèê

SPI2->I2SPR|=I2SMCKOE(1);//âûõîä Ìàñòåð êëîêà

(I2S2ext->I2SCFGR)=0;

I2S2ext->I2SCFGR|=SPI_I2SCFGR_I2SMOD;//âêëþ÷èë I2S

I2S2ext->I2SCFGR|=SPI_I2SCFGR_DATLEN_0;//24áèò äàííûå

I2S2ext->I2SCFGR|=SPI_I2SCFGR_CHLEN;//32áèò äëèíà äàííûõ 

I2S2ext->I2SCFGR|=I2SCFG(0);//�åæèì Ñëýéâ - òðàíñìèòòåð

SPI2->CR2|=SPI_CR2_RXDMAEN;//DMA

SPI2->I2SCFGR|=SPI_I2SCFGR_I2SE;//âêëþ÷èë SPI

delay(5);

I2S2ext->I2SCFGR|=SPI_I2SCFGR_I2SE;//âêëþ÷èë SPI

}