STM32F407 SPI RXNE flag bit clears automatically

gopi natarajan · ‎2017-09-10

Posted on September 10, 2017 at 19:11

Hi all, I am using STM32F407 Discovery board and trying to initialize and retrieve the data from the on-board accelerometer. I have properly initialized the PA5, PA6 & PA7 as SCLK, MISO & MOSI pins respectively. The SPI1 is also properly initialized with MSTR, CPOL, CPHA, SSI, SSM & SPE bits set in CR1 and SSOE bit set in CR2 (First, i would like to use polling mode for Data Transmission/Reception).

After the initialization part gets over, I try to read the FIFO status register of the accelerometer by sending its corresponding address byte following a dummy byte to retrieve the register value and end up with either the Overrun flag bit set in the Status register (SR becomes 0x42 indicating OVERRUN and TXE bits are set) or the data byte is received in the SPI1->DR and the RXNE bit is set, but gets cleared even before the controller tries to read the status register. As a result, my polling condition gets struck in a continuous loop that will never break.

Kind note:

1. As this is an example I am trying to build, I skipped to exit the continuous loop by providing some time deviation or performing the SPI Read/Write operation via TXE and RXNE interrupts.

2. Compiler is CooCox CoIDE V1.7.8. with GNU compiler.

3. I verified the RXNE bit gets cleared even when I perform a single step debug.

.

Vangelis Fortounas · ‎2017-09-10

Posted on September 10, 2017 at 19:51

Hello!

>>> 'by sending its corresponding address byte following a dummy byte to retrieve the register value'

The overrun flag is set in case you receive one byte and the DR has allready an unreaded byte.

You transmited a byte but didn't read the received byte. Then you transmited a dummy byte and the received data caused the overrun.

A suggested sequence to transmit-receive a single byte is

Poll(wait) for TXE until set. Send a byte by writing to DR . Poll(wait) for RXNE bit until set. When RXNE bit is set, read the DR .

You can keep the received byte or discard it(dummy byte as you wrote)

>>> '3. I verified the RXNE bit gets cleared even when I perform a single step debug.'

Is your debuger provide real time register information when program is halted?(step)

Regards.

vf

gopi natarajan · ‎2017-09-10

Posted on September 10, 2017 at 21:16

Hi vangelis,

>>> 'A suggested sequence to transmit-receive a single byte is

Poll(wait) for TXE until set. Send a byte by writing to DR . Poll(wait) for RXNE bit until set. When RXNE bit is set, read the DR . '

I follow this method to receive data. Unfortunately, my question got posted before I complete my whole question.

>>> '

Is your debuger provide real time register information when program is halted?(step)'

To my knowledge, the debugger is providing real time register information when a breakpoint is hit or when i pause the debug process in a random time during code execution.

Let me explain a concept which I think would have reset the RXNE flag bit. As per the reference manual, the RXNE bit will be cleared by reading the SR followed by reading the DR register. So, If i put a break point in a line just next to the line which transmits the dummy value, I am able to see the RXNE bit is set. This happens as the debugger reads all the register values from SPI and other peripherals and dump them into the debug 'Peripherals' window. This means, the debugger reads the SR register and the DR in step by step manner.

Will this process of dumping the SPI SR register and the DR register by the CooCox IDE clear the RXNE bit during debugging.?

Kind note. I even tried 'Instruction single step mode (execution of assembler instructions for each single step execution)' and found that the RXNE bit gets cleared even if the code didn't read the SR and the DR registers.

Vangelis Fortounas · ‎2017-09-10

Posted on September 10, 2017 at 22:18

Hi!

>>>Will this process of dumping the SPI SR register and the DR register by the CooCox IDE clear the RXNE bit during debugging.?

The answer is yes! Just leave your code to handle the transaction and not interfere between the SR and DR read.

If you want to observe the flags make some code to do this.

Rgrds

vf