STM32F4 does not self-reset on power up; BOOT0 is tied to GND

[geof]

Posted on April 16, 2013 at 22:58

Hello,

I'm using an STM32F415 in an LQFP64 package on a new PCB design. BOOT0 is tied to ground. I can program the STM32 (using IAR and the ISP designed by ST) and get it to run using the IDE. The NRST pin is floating on the PCB, though connected to the JTAG of course. However when I remove the ISP the processor no longer resets on it's own. I can, though, get the processor to run by shorting NRST to GND. I am pretty sure this is something to do with the PCB design itself- I have another ''old'' PCB design, also using the same processor, and some code that runs fine on that old PCB design. (e.g. it resets on it's own just fine.) But when I take that known code and program it into the new PCB design I get the same result- it runs when the ISP is connected and prompted in the IDE, and runs when I manually short the NRST to GND, but does not reset to start running on it's own. I have already fabricated a second of the ''new'' PCB designs to rule out a bad processor. Same result. I even tried physically desoldering and bending up the NRST pin to eliminate the possibility of capacitive (or whatever) loading on that pin. Same result. I do have the requisite 0.1uF bypass capacitors, 2.2uF regulator capacitors for VCAP, and 4.7uF big bypass capacitor, and VDDA and VSSA are connected respectively to VDD and GND. This is for both the troublesome ''new'' and verified ''old'' PCB designs. BOOT0=GND on both designs. Has anyone experienced something like this before, or have any suggestions? Thanks! Geof

[Tesla DeLorean]

Posted on April 16, 2013 at 23:13

IRST, you mean NRST?

Does NRST go high? Or driven high externally? Do the supplies ramp slowly? What about PB2/BOOT1? VBAT, PC13, PC14, PC15 If BOOT0 is high at reset, can you access the System Loader via USART1 or USART3? ie Send 0x7F at 9600 8E1, and get an 0x79 response.

[geof]

Posted on April 16, 2013 at 23:40

Clive-

Thank You for your response! Yes, I mean NRST. I edited the above post to clarify that. For this application, once the ISP is removed the NRST is left floating, e.g. I am relying on the internal pull-up. I've attached the oscilloscope trace of VDD (yellow) and NRST (blue). You can see VDD ramp up towards the operating voltage of 3.3V- this is the regulator charging the bypass capacitors. When VDD reaches about 1.8V, the NRST line jumps up to about the same voltage. Then VDD and NRST asymptotically settle to 3.3V, the desired operating voltage. NRST just hangs there. And just to make it clear, if I use a wire to short NRST to GND, the processor starts running. BOOT1 is floating right now, but I get the same result when BOOT1 is GND (already tried that). The data sheet though seems to imply that BOOT1 is irrelevant if BOOT0 is GND. Just to make it clear, BOOT0 is soldered e.g. fixed to GND. VBAT has it's own 0.1uF bypass capacitor and is tied to VDD. PC13, PC14, and PC15 are not connected e.g. they are floating. I don't think that should be a problem though since these same three pins (PC13-15) are floating on the PCB that works fine. More info that might help: When the PCB is powered up, it draws about 25mA. This is just the regulator and the processor. When I get it to run (by shorting NRST to GND) the current draw increases to about 46mA. Geof ________________ Attachments : tek00000.jpg : https://st--c.eu10.content.force.com/sfc/dist/version/download/?oid=00Db0000000YtG6&ids=0680X000006HtXV&d=%2Fa%2F0X0000000aRT%2FjypOQPoHiANgnhCwAN.RaLpSSwNiBJM9UpSjlP9AkUI&asPdf=false

[John F.]

Posted on April 17, 2013 at 09:25

Geof,

You wrote, ''I even tried physically desoldering and bending up the NRST pin to eliminate the possibility of capacitive (or whatever) loading on that pin.'' The Recommended NRST connection includes a 100n capacitor to ground (which will affect relative timing).

[geof]

Posted on April 17, 2013 at 15:03

Hi John,

PROBLEM SOLVED! I added a 0.1uF cap between NRST and GND and the processor starts itself normally. Thanks a million!!! It is interesting though that none of our other board designs with the STM32F4 have such a capacitor and they start up just fine. Geof

[stst9184]

Posted on July 20, 2015 at 10:58

Hi,

I have similar effects. Our device ramp slowly. We use pins PC13, PC14, PC15. Why do you ask? what does it mean?

[Tesla DeLorean]

Posted on July 20, 2015 at 15:54

Because they are in the low power domain, and have very low current drive. Supplied by VBAT when primary supply is absent.

The VDDA is used by the internal power-on-reset circuit. Driving NRST by an external push-pull driver will break the device's reset mechanism.

[stst9184]

Posted on July 20, 2015 at 17:27

How is the VDDA used ?

I wrote an  another question about it here : https://my.st.com/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/Flat.aspx?RootFolder=/public/STe2ecommunities/mcu/Lists/cortex_mx_stm32/VDDA%20starts%20after%20VDD&currentviews=11 and not yet answered.

[Tesla DeLorean]

Posted on July 20, 2015 at 17:39

The POR thresholds against it? The PLL/VCO use it?

[pavel]

Posted on July 28, 2015 at 17:07 Hello, I have question about behaviout nRST pin vhen uP SM32F427 goes from STANDBY mode. On my PCB board I have code where I can call function standby, and I will set uP to STANDBY, when I wake up processor, and check  RCC_CSR, there is no set bit PINRSTF. But in documentation about Power rest for uP STM32F427 section 6.1.2. (Power Reset) is mentioned '' A power reset is generated when one of the following events occurs: 1. Power-on/power-down reset (POR/PDR reset) or brownout (BOR) reset 2. When exiting the Standby mode A power reset sets all registers to their reset values except the Backup domain (see Figure 4)

These sources act on the NRST pin and it is always kept low during the delay phase. The

RESET service routine vector is fixed at address 0x0000_0004 in the memory map. The system reset signal provided to the device is output on the NRST pin. The pulse generator guarantees a minimum reset pulse duration of 20 μs for each internal reset source. In case of an external reset, the reset pulse is generated while the NRST pin is asserted low. '' But when I také oscilloscope, theri is nothich change ''no pulse  ''1''''0''''1'' '' on nRST pin. There is still ''1'' and in RCC_CSR is not set PINRSTF. But acording to documentation wake up change nRST pin and PINRSTF too. Could ypu please explain me why? Thank you very much