STM32F4 DMA REQ and ACK for External DMA

[Zaher]

Posted on October 21, 2017 at 02:13

I'm trying to interface my STM32F407 MCU with a peripheral device that has independent DMA/MPU interfaces. The MPU interface is available in two modes (68 and 80) and the data bus width is available in 8-bit and 16-bit mode. The device can be configured to use the same bus for both of the DMA and the MPU, which I believe makes it easier to access the device utilizing the FSMC peripheral.

As far as the MPU interface is concerned, I'm not sure which mode works better in this situation as I did not try it yet (Muxed PSRAM vs LCD Interface), but seems like the LCD Interface is the way to go. 

My problem is how to adapt the REQ and ACK signals of the DMA controller on the peripheral chip while the STM32F4 maps requests only from internal peripheral of the MCU itself? Is this something ST has not taken into consideration for their Cortex-M devices? 

Any ideas? 

Thanks!

[Tesla DeLorean]

Posted on October 21, 2017 at 02:59

It is not 1980 any more, if you want some DACK/DRQ model consider using an FPGA/CPLD, memory device, and FSMC connectivity to that device. ST chose to implement a simple DMA block which they did a step-and-repeat of to service their peripherals.

Look at the DCMI interface for rapid input. FSMC for bus like input/output.

You can configure the DMA to use the GPIO pins for input/output, triggering a channel on DMA2 via a TIMx_CHx trigger, ie set pin on TIM for input capture, and have the CCx of that capture to trigger the DMA.

The destination could also be to memory mapped on the FSMC bus.

Look at FIFO devices, like the AL422B

http://www.averlogic.com/AL422B.asp

 

[Zaher]

Posted on October 21, 2017 at 17:54

LOL! Of course it's not 1980 anymore, Mr. Clive, however, I do not think the DREQ/DACK mechanism is something restricted to the 80s era. In fact, many new devices still incorporate the same mechanism for their DMA controller, and I just don't see how a DMA controller is useful without these signals, as the mem-to-mem scenario is very common. Even on an FPGA/CPLD, a scatter-gather DMA IP core still has the same mechanism, though I do not have any experience with FPGAs and CPLDs and I never used one in any of my projects yet.

On the other hand, I see that you were more accommodating and acknowledging to the very same topic few years ago:

https://community.st.com/0D50X00009XkhgoSAB

And here I quote you: '

The lack of a proper ACK/REQ DMA interface is one of the missed opportunities in the STM32 designs.

'

But the solution proposed is very helpful and seems to be the one I need to solve the issue.

Thank you again for taking care everything over here!

Zaher