STM32F334 24MHz+ PWM not stable

[previn]

Posted on December 14, 2016 at 21:20

I am having trouble getting a stable PWM of greater than 24MHz on the STM32F334 discovery board. Below are the configurations I have:

8MHz external Oscillator

SYSCLK = 72MHz

(PLLMUL * 8MHz, PLLMULL = 9)

HRTIM source = 144MHz

(SYSCLK * 2)

HRTIM frequency =

4.608GHz

(DLLMUL * 144MHz, DLLMUL = 32)

The instability appears as though the signal stays high for 1 full period, and then operates at the correct frequency, repeatedly. This happens more frequently as the frequency increases further beyond 24MHz.

The interesting thing is that 36MHz is stable, could be because it is a factor of SYSCLK. 

Has anyone else seen this problem?

#stm32f3-discovery #stm32f3 #stm32f334

[previn]

Posted on December 15, 2016 at 23:07

Could this be due to the access latency of the embedded flash? Does the HRTIM1 peripheral have a limited access time of the compare registers?

Mentioned in the reference manual:

Bits 2:0 LATENCY[2:0]: Latency

These bits represent the ratio of the SYSCLK (system clock) period to the Flash access time.

000: Zero wait state, if 0 < SYSCLK≤ 24 MHz001: One wait state, if 24 MHz < SYSCLK ≤ 48 MHz010: Two wait sates, if 48 < SYSCLK ≤ 72 MHz

[Tesla DeLorean]

Posted on December 16, 2016 at 00:24

How in your scenario is FLASH being used with respect to the timer? Are you trying to generate modulating patterns? At what rate?

If you are aggressively reprogramming the timer perhaps you can go into more detail about that. Can you use RAM? Can you use DMA?

The peripheral is going to have access constrained by the APB or AHB to which it is attached, you can reasonably expect reads to take several cycles, and writes to be posted to write buffers.

[previn]

Posted on December 16, 2016 at 02:31

I'm setting the HRTIM registers CMP1 (to output set), CMP2 (to output reset) & CMP4 (to HRTIM reset).

e.g. I want 30MHz at 50% duty cycle:

HRTIM frequency = 4.608GHz4.608GHz/30MHz = 153.6 HRTIM ticks in one 30MHz period, therefore:

CMP1 = 153/2 = 76

CMP2 = 153

CMP4 = 153

After setting the registers, I then enable the PWM output and that's it (no aggressive reprogramming of the timer). I've even halted the ARM processor (using a breakpoint in debugger), and the PWM continues to run with the jitter.

I am eventually aiming to produce a PWM that ranges from 10MHz to 30MHz. I might be adding confusion with the FLASH, but that's the only thing I've found that remotely corresponds with 24+MHz producing jitter.

Side note, are peripheral registers (accessed by the respective peripheral) constrained by limitations of the AHB/APB bus, or are they directly located with the peripheral itself and doesn't require the bus matrix to run on its own?

[Tesla DeLorean]

Posted on December 16, 2016 at 19:56

Most peripherals clock internally at the APB rate, being a synchronous design. The TIM peripherals are a slight exception where the counter can be 2X the APB clock (ie taken one tap earlier from the divider chain)

The HRTIM may have other things going on, it is not a peripheral I use, but I don't think it should jitter based on code execution if programmed and left alone.

[previn]

Posted on December 19, 2016 at 03:43

Thanks, I'll continue to look into the HRTIM peripheral.