STM32F303 - disabling DMA during transfer

[jcphillips]

Posted on March 21, 2013 at 04:08

I'm having difficulty getting deterministic behavior when disabling a DMA transfer in progress.  I'm using DMA to feed the USART 2 transmitter from a buffer.  When I need to queue up more data for the transmitter, I'd like to

• disable the DMA channel
• use the DMA channel counter (CNDTR) to determine how many bytes were sent
• shift the remaining bytes to the start of the buffer and append the new bytes
• setup the DMA controller to transfer the new buffer and enable it.

I'm getting repeated (and occasionally missing) bytes out the USART using this method, as if CNDTR is not reliable after disabling a transfer in progress.  I can't seem to find any documentation on what to expect when disabling a DMA channel in the middle of a transfer. Can this be done in a deterministic way? Is there a flag or indication I should wait for after disabling the DMA channel? (Note that Transfer Complete is not set after the channel is disabled). Most interesting thing:  This same code worked with the STM32F103. -jcp

[waclawek.jan]

Posted on March 21, 2013 at 11:28

> Is there a flag or indication I should wait for after disabling the DMA channel?

While the description of the 'F3 DMA is different from the 'F2/'F4, I'd risk a guess that they stem from the same root. Thus, I'd try the procedure outlined in the 'F2/'F4 manual, namely after writing zero to ENABLE bit, reading it back until it reads zero. > (Note that Transfer Complete is not set after the channel is disabled). Did you check that? If it's true the DMA units are similar, it should be set (after EN readback goes to zero as described above). JW

[Tesla DeLorean]

Posted on March 21, 2013 at 15:18

Seems like a lot of unnecessary faffing around, why not just chain another DMA transaction when you get the TC interrupt?

[jcphillips]

Posted on March 21, 2013 at 21:10

That is probably what I'll end up having to do.  I've already verified that waiting for each transfer to complete results in correct operation.  I was trying to avoid rewriting existing code and having (what I feel is) the added complexity of additional ISRs in my application.  It would also be reassuring to know that DMA transfers can be interrupted with predictable results.

This evening, I'll try the suggestions made by JW before embarking on a rewrite. -jcp

[jcphillips]

Posted on March 22, 2013 at 05:19

So, here is the scoop.   When the DMA channel is disabled by clearing the EN bit in its CCR register during a transfer, the bit is cleared immediately.  At least, it is always faster than the few cycles it takes for a single branch and read of the CCR register (that is how the C compiler generated it).  Also, when the DMA channel is disabled during a transfer in this way, the Transfer Complete Flag is not set in IFCR.  All of this would be fine if CNDTR could be used to correctly calculate the number of bytes transferred.  But it seems that is not the case.

Just for reference, I'm running the STM32F303 (Rev Y) at 60Mhz (PLL driven from HSI) with APB1 and APB2 at 30MHz.  USART2 is transmitting at 115200. Now, on to a different implementation. -jcp

[waclawek.jan]

Posted on March 22, 2013 at 08:21

So it appears that the 'F3 DMA unit is indeed different from the 'F2/'F4. Thanks for letting us know that.

JW