Posted on July 13, 2015 at 02:48I'm trying to configure my sys clock to be 72MHz but I'm not clear on how to do this. In the system file has this:
/* PLL configuration: PLLCLK = HSI/2 *16 = 64 MHz Max frequency on PLL HSI mode*/
RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16);
But in this migration document it says the F30xx should be capable of 72MHz.
In STM32F30xxD/E, we can reach the maximum system clock 72 MHz when PLL is systemclock source and PLL clock source is the HSI. In STM32F1 and other STM32F3 seriesdevices, when PLL clock source is the HSI, the maximum system clock value is 64 MHz.''
Which of these two is correct?
