Posted on December 01, 2015 at 18:50
Well it doesn't strike me as a very robust solution.
In terms of the mapping of RAM at zero at reset, one should just be able to carve out 8-bytes from the linker's use of RAM, by advancing the base of RAM to 0x20000008, and shrinking the size by 8 bytes. Then you'd copy the first TWO vectors from the FLASH into those locations at 0x20000000, so if the processor starts there it fetches the SP/PC pair from RAM, and then proceeds to execute from FLASH.
The F1 is a bit problematic, it's been many years since I did a through evaluation, but as I recall some odd things happen with RAM execution, that ST has never explained very well. It would appear that it executes some other code first, and then jumps to a specific Reset Handler address at the end of the vector table. See the GNU/GCC startup_stm32f1xx.s files for the only real admission that something odd goes on. There is an opcode placed at the end of the vector table, that indirects through the +4 vector to the PC actually pointed too in the table. If this is still the case, you'd need to carve out space for the entire vector table, and copy it all to the base of RAM.
...
.equ BootRAM, 0xF108F85F
...
/******************************************************************************
*
* The minimal vector table for a Cortex M3. Note that the proper constructs
* must be placed on this to ensure that it ends up at physical address
* 0x0000.0000.
*
******************************************************************************/
.section .isr_vector,''a'',%progbits
.type g_pfnVectors, %object
.size g_pfnVectors, .-g_pfnVectors
g_pfnVectors:
.word _estack
.word Reset_Handler
.word NMI_Handler
.word HardFault_Handler
.word MemManage_Handler
.word BusFault_Handler
.word UsageFault_Handler
.word 0
.word 0
.word 0
.word 0
.word SVC_Handler
.word DebugMon_Handler
.word 0
.word PendSV_Handler
.word SysTick_Handler
.word WWDG_IRQHandler
.word PVD_IRQHandler
.word TAMPER_IRQHandler
.word RTC_IRQHandler
.word FLASH_IRQHandler
.word RCC_IRQHandler
.word EXTI0_IRQHandler
.word EXTI1_IRQHandler
.word EXTI2_IRQHandler
.word EXTI3_IRQHandler
.word EXTI4_IRQHandler
.word DMA1_Channel1_IRQHandler
.word DMA1_Channel2_IRQHandler
.word DMA1_Channel3_IRQHandler
.word DMA1_Channel4_IRQHandler
.word DMA1_Channel5_IRQHandler
.word DMA1_Channel6_IRQHandler
.word DMA1_Channel7_IRQHandler
.word ADC1_2_IRQHandler
.word USB_HP_CAN1_TX_IRQHandler
.word USB_LP_CAN1_RX0_IRQHandler
.word CAN1_RX1_IRQHandler
.word CAN1_SCE_IRQHandler
.word EXTI9_5_IRQHandler
.word TIM1_BRK_IRQHandler
.word TIM1_UP_IRQHandler
.word TIM1_TRG_COM_IRQHandler
.word TIM1_CC_IRQHandler
.word TIM2_IRQHandler
.word TIM3_IRQHandler
.word 0
.word I2C1_EV_IRQHandler
.word I2C1_ER_IRQHandler
.word 0
.word 0
.word SPI1_IRQHandler
.word 0
.word USART1_IRQHandler
.word USART2_IRQHandler
.word 0
.word EXTI15_10_IRQHandler
.word RTCAlarm_IRQHandler
.word USBWakeUp_IRQHandler
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word 0
.word BootRAM /* @0x This is for boot in RAM mode for
STM32F10x Low Density devices.*/
Perhaps someone at ST can give you a better explanation.
