Posted on February 04, 2013 at 04:05It appears the TIM4 OC interrupts on CH2 results in occasionally missing an Update (overflow) interrupt.
The situation is a 1 PPS GPS pulse triggers the TIM4 CH1 input capture. The 16 bit counter time is extended by adding 0x10000 to a 32b time count upon each overflow interrupt and loading the IC register into the lower 16b of the extended time count upon an IC. The case where both flags are on when the isr executes is handled by adding an overflow count if the IC less than 32767, and skipping otherwise. This will run for days without missing.
The CH2 output compare was added with the goal of generating 64 interrupts that are accurately synchronized with the GPS 1 PPS. The 16b register requires adding increments to the OC register upon each OC interrupt to span the 1/64th sec. The increment is computed from the number ticks between the 1 PPS input captures. When the CH2 interrupt flag is enabled the time between 1 PPS interrupts occasionally is 65536 too small indicating that an overflow count was missed.
The following leads me to the notion that bus timing is involved in the following experiment. First, the following code causes many cases of missing overflow counts-
TIM4_CCR2 += ticks /1280;
(Where 'ticks' would be something like 64000253).
However, the following runs for long periods (e.g. a hour) of time before an error-
x = ticks / 1280;
y += x;
TIM4_CCR2 = y;
Another, possibly related curiosity, is that for the input capture of 1 PPS times (and the OC not running nor involved) there are four situations for for the status register when the isr is executed--
01 overflow only
10 input capture only
11 both on (requiring a test to see which was first)
00 Which appears to be an overflow and IC capture coinciding, i.e. the correct result is if this is handled as a 11 case.
I observed the '00' case 11 times over approximately a 12 hour period.
My hunch is that the problem when the OC was added has a similar cause as the '00' input capture case.
BTW, I tried running the bus at 1/2 the speed that the problem remained. Also I do a readback of the SR before exiting the isr to avoid tail-chaining (and tail-chaining would result in extra, not missing, counts).
Any ideas as to what is causing the OC to disrupt the overflow and IC interrupts?
