2022-06-19 08:30 AM
2022-06-19 08:53 AM
The Reference Manual RM0008 should detail the NVIC, and CAN registers. The Data Sheet options specific to the part you're using
2022-06-19 11:23 AM
Thank you for the reply, however:
Maybe, the easy way to ask this is,
To Enable interrupt for CAN Bus Receive, I need to use NVIC_ISERx register.
BUT..
All bits in the NVIC_ISERx register are labelled 'rs'. (Ref Manual + Programming manual)
(Datasheet does not look at register structure - its more general than the Ref Manual + Prog manual)
I dont know which of the register bits relates to the CAN RECEIVE INTERRUPT as they are all called 'rs'
2022-06-19 11:52 AM
There are two RX interrupts, one for each FIFO, NVIC bit 20 and 21
As I recall this F1 part the RX0 overlaps with USB_LP_IRQ (you can either use CAN or USB, as they share a FIFO RAM)
2022-06-19 12:29 PM
Yes the blue pill board is old. I think that you can use CAN or USB, bot not both at the same time.
Ah, so if I set bit 20 of the NVIC_ISERx register. this will ENABLE the CAN1_RX0 interrupt for FIFO_0?
2022-07-06 09:08 AM
Hi,
Can anyone confirm that below contains the correct code for ENABLING the FIFO/ CAN receive INTERRUPTs for:
(1)- CAN peripheral
(2)- NVIC - the CAN_RX0/ FIFO 0 interupt
(3)- Is the code in (3) equivalent to the code in (2)
(1) -
CAN1->IER |= CAN_IER_FMPIE1;
CAN1->IER |= CAN_IER_FMPIE0; // CAN_RX0
(2) -
NVIC_EnableIRQ(USB_LP_CAN1_RX0_IRQn);
NVIC_EnableIRQ(CAN1_RX1_IRQn);
NVIC_EnableIRQ(CAN1_SCE_IRQn);
(3) - Do the lines below do the same as the NVIC_EnableIRQ lines
NVIC->ICER[0] |= (NVIC_ICER_CLRENA_20 | NVIC_ICER_CLRENA_21);
NVIC->ISER[0] |= (NVIC_ISER_SETENA_20 | NVIC_ISER_SETENA_21);
I would appreciate your help with this
Regards,