STM32F103 low power (stop) mode excessive current draw - GPIO state?

[jim239955_stm1_st]

Posted on November 17, 2009 at 15:15

STM32F103 low power (stop) mode excessive current draw - GPIO state?

[jim239955_stm1_st]

Posted on May 17, 2011 at 13:28

I am having problems with stop mode for an STM32F103 processor. I expect to get around 120 uA but am somewhere around 1.6 mA. The problem appears to be the state of my GPIOs when entering stop.

On

http://www.st.com/mcu/forums-cat-8407-23.html

the recommendation is to set the GPIO lines to analog inputs - I believe the 50MHz speed is ignored for analog inputs. Anyway, I am setting all of the GPIOs to analog inputs. And on

http://www.st.com/mcu/forums-cat-8942-23.html

it says ''Also, check for any inputs that are driving against any pull-ups activated on the pins. Similarly, check for outputs driving against pull-downs on external devices.'' However, it does not go on to say what to do if you have pull-ups. I am hoping for recommendations on what to do with GPIO pins in stop mode. I have a number of pull-ups and downs on GPIO pins. I have to keep two ports (D and E) active to deassert some lines and accept external interrupts. I am attempting to put the remaining lines in a dormant state. The remaining ports are (A, B, C) are inactive (clock off). At one point when I deassert a GPIO the current goes up ~ 1mA so I have some sort of cross talk or other effect. This current increase accounts for most of my over current situation. Any help greatly appreciated. Thanks.

[johnfitzgerald9]

Posted on May 17, 2011 at 13:28

Hello again,

If you have an external pull up resistor, keep that GPIO high. If you have an external pull down resistor, keep that GPIO low. If you have an external pull up resistor, say 3k3 to 3.3V and pull it low externally then about 1mA IS going to flow isn't it. If you deassert a GPIO programatically then you aren't in STOP mode. Can't be because the program must be running. As far as the rest goes ... The manual says, Stop mode The Stop mode is based on the Cortex-M3 deepsleep mode combined with peripheral clock gating. The voltage regulator can be configured either in normal or low-power mode. In Stop mode, all clocks in the 1.8 V domain are stopped, the PLL, the HSI and the HSE RC oscillators are disabled. SRAM and register contents are preserved. In the Stop mode, all I/O pins keep the same state as in the Run mode. To further reduce power consumption in Stop mode, the internal voltage regulator can be put in low-power mode. This is configured by the LPDS bit of the Power control register (PWR_CR). If Flash memory programming is ongoing, the Stop mode entry is delayed until the memory access is finished. If an access to the APB domain is ongoing, The Stop mode entry is delayed until the APB access is finished. In Stop mode, the following features can be selected by programming individual control bits: â—� Independent watchdog (IWDG): the IWDG is started by writing to its Key register or by hardware option. Once started it cannot be stopped except by a Reset. See Section 17.3 in Section 17: Independent watchdog (IWDG). â—� real-time clock (RTC): this is configured by the RTCEN bit in the Backup domain control register (RCC_BDCR) â—� Internal RC oscillator (LSI RC): this is configured by the LSION bit in the Control/status register (RCC_CSR). â—� External 32.768 kHz oscillator (LSE OSC): this is configured by the LSEON bit in the Backup domain control register (RCC_BDCR). The ADC or DAC can also consume power during the Stop mode, unless they are disabled before entering it. To disable them, the ADON bit in the ADC_CR2 register and the ENx bit in the DAC_CR register must both be written to 0. Does any of that work?

[akaiser9]

Posted on May 17, 2011 at 13:28

Is anything having its power removed connected to active ports? Ports driven or pulled high internally could supply power to the device through the pin protection diodes.

[jim239955_stm1_st]

Posted on May 17, 2011 at 13:29

Just a quick reply to say thanks. For some reason the automated email did not get to me so I was not away of this greatly appreciated input. I will be going through this in detail as soon as possible.

[jim239955_stm1_st]

Posted on May 17, 2011 at 13:29

I have reduced the problem to an experiment with one GPIO line. All GPIO lines are in the power up default state: analog input. I enable one port clock. And one port pin PE.11 is setup as a push/pull output, 50 MHz. All the rest remain in the default state. That single pin is attached to a transistor. That's all. If I de-assert the line the current drops ~1 mA. If I assert the line the current increases ~1 mA. If I enter stop mode with the line asserted the current draw includes this extra 1 mA. Since PE.11 is kept in the same state in stop as in run mode, this seems to follow.

Of course there are many GPIOs involved with the system. I configure as many of them as I can as analog inputs. The last step before entering stop mode is to assert this PE.11. Enabling PE.11 increases the current draw ~1 mA. When I am in stop mode the current draw is 1.2 mA. .2 mA is the target. So, in my mind, PE.11 is the culprit. I am being told this 1 mA increase is because I do not have the other GPIO lines in the appropriate state. But if they are in analog input mode the pull up/down resistors should not matter. Perhaps the interaction between the 6 or 7 GPIO lines is the problem. I just seem stuck on the PE.11 experiment. What is in common here is that all of the unused GPIO pins are configured as analog inputs. So perhaps this is true. I trying to get some context to approach the problem. Hopefully your questions will help me see the problem in a different light. I seem to be stuck at this point. As always, thanks for the help.

[akaiser9]

Posted on May 17, 2011 at 13:29

I assume ''assert'' means setting the pin to high level.

If an output pin has to supply 1mA to the device attached, such as a bipolar transistors with a 2.7KOhm base resistor, this won't change by entering stop mode. So it all boils down to the question, how to achieve the required functionality with a different external circuit.

[jim239955_stm1_st]

Posted on May 17, 2011 at 13:29

I have fixed this problem. There was a single GPIO tied to a resistor that accounted for about 1.4 mA. That left me with a 210 uA draw that was still too high. What I had to do was setup all GPIOs as analog inputs in stop mode. I was already doing that for the GPIOs I was using. When I reconfigured the unused GPIOs as analog inputs the current draw dropped to about 80 uA - the board with the processor removed draws ~50 uA. The default GPIO state is floating input which can cause some current draw. That was a secondary problem. I spent a lot of time looking in the wrong places.

Hope this helps someone.