2015-06-04 11:28 AM
I can't find the internal oscillator accuracy anywhere in the datasheet or the reference manual. If I have the sysclk set at 48MHz from the internal osc. what are the limits of what that sysclk may actually be?
#data-sheet2015-06-04 12:31 PM
Which internal oscillator? If you mean HSI (which is probably what you mean, given that's the only one good to drive the PLL), then try to look at the ''HSI oscillator characteristics'' table in the datasheet.
JW2015-06-04 01:26 PM
You're driving the HSI +/-5% into a X6 PLL to get 48 MHz, expect the error percentage it be about the same or degrade. ie It will scale but not improve.
2015-06-04 01:30 PM
Thank you!
2015-06-04 01:47 PM
I translated (3) as meaning at a specific temperature and voltage, and with effort, you could get to +/-1%
With significantly more effort, where you characterize the part in your board over temperature, and back, and perhaps over voltage, you might get somewhere in the 1-5% range, or at least understand the behaviour, and perhaps manage it. I think this ''calibration'' is a single point thing, and not some feedback term in a temperature loop. Real TCXO solutions are significantly more complicated.2015-06-04 01:55 PM
I believe the idea is more to calibrate the HSI runtime against a reference, such as LSE if present, or baudrate of received USART stream from a known precise source, or similar such.
I wouldn't hold my breath, though. The ''tuning step'' is said to be 1% in the table above so you can't get better anyway; and last time I looked at the HSI (although on a F4) it was not only imprecise in the long run but also significantly jittery. JW