Skip to main content
Simon Schulz
Simon Schulz
Associate II
April 6, 2017
Question

STM32F0 SPI DMA triggered by Timer compare match

  • April 6, 2017
  • 5 replies
  • 1078 views
Posted on April 06, 2017 at 20:25

Hi!

I have a question regarding the stm32f0 DMA engine. I am using an stm32f0discovery MB1034B evaluation board.

I have the following setup:

The SPI dma is configured to transmit 3 bytes from memory to the spi peripheral. Let's say I transfer bytes 0x0A 0x0B 0x0C.

If I trigger the dma transfer via the spi tx dma en flag i cann see my three bytes on the spi bus (0x0a 0x0b 0x0c).

Then the DMA transfer completet isr fires. All fine.

Now i want to trigger the dma transfer by a timer1 ch2 compare match (which is as well on dma1 channel 3).

The thing is I can only see single byte transfers. On cc match number one I see 0x0a.

One second later (on the second compare match) I see 0x0b. Another second later I see 0x0c.

Then the DMA transfer completet isr fires.

Why does the timer only initiate single transfers? I expected to see the same transfer as when triggering the spi manually?!

Any hints?

    This topic has been closed for replies.

    5 replies

    waclawek.jan
    waclawek.jan
    Super User
    April 7, 2017
    Posted on April 07, 2017 at 11:15

    That's how DMA works: one trigger (request), one transfer.

    If you trigger DMA from SPI_Tx, there is one transfer every time the SPI_SR.TXE flag goes high. As the data written to SPI_DR are transferred to the shift register when it is/gets empty, there's one such trigger each time this transferr happens.

    If you trigger it from timer, there's one transfer every time the compare happens.

    JW

    Simon Schulz
    Simon SchulzAuthor
    Associate II
    April 7, 2017
    Posted on April 07, 2017 at 19:39

    Ah now I understand. I was not aware that the SPI txe flag retriggers the dma for all following bytes.

    That makes perfectly sense now, thanks!

    Simon Schulz
    Simon SchulzAuthor
    Associate II
    April 10, 2017
    Posted on April 10, 2017 at 22:36

    Is there a way to start a multi-byte spi dma from a compare match? That way I would not have any issues with the interrupt latency.

    Tesla DeLorean
    Tesla DeLorean
    Guru
    April 11, 2017
    Posted on April 11, 2017 at 02:38

    Real problem there is aligning the TIM pulses with the transmit buffer being empty.

    You might be able to use an advanced timer in repetition mode to fire CCx 3 times.

    Consider an FPGA/CPLD with a 24-bit shift register triggered by whatever event it is you want to align against. Or generate SPI clocks for a slave feed via a DMA buffer/loop

    Tips, Buy me a coffee, or three.. PayPal Venmo (See Profile) Up vote any posts that you find helpful, it shows what's working..
    Jan Waclawek
    Jan Waclawek
    Visitor II
    April 11, 2017
    Posted on April 11, 2017 at 06:25

    Real problem there is aligning the TIM pulses with the transmit buffer being empty.

    Not that of a problem in case of master SPI, unless you insist the clock being perectly continuous. Both the SPI a Timer work out of a common clock source so things are perfectly synchronous.

    You might be able to use an advanced timer in repetition mode to fire CCx 3 times.

    +1

    Alternatively, at a cost of 2 DMA channels you can fill a 'conventional' SPI-triggered DMA's control register by a TIM-triggered DMA.

    JW

    Terms & ConditionsAccessibility statement