2015-08-02 10:48 AM
Hi,
In setup for STM32F746G-DISCO, FW_F7 V1.1.0
In Clock Configuration, when selecting PLLSAIP @ CLK48 Clock Mux for USB,
it generates code
PeriphClkInitStruct.PLLSAI.PLLSAIP = RCC_PLLP_DIV4;
which should be
PeriphClkInitStruct.
PLLSAI
.
PLLSAIP
= RCC_PLLSAIP_DIV4;
2015-08-17 01:44 AM
Dear user,
Thank you in reporting this issue. The bug will be resolved in release 4.10.