STM32427 with CubeMX

john239955_st · ‎2015-05-23

Posted on May 23, 2015 at 11:34

I have a board with a 32 bit SRAM and have used CubeMX to configure a 32 bit data bus, a 10 bit Address bus with a Chip select of NE1.

Briefly, Cube has produced the MX_FMC_Init(); file with settings as follows:-

hsram1.Init.NSBank = FMC_NORSRAM_BANK1;

also ..... MEM_BUS_WIDTH_32 etc.

I have used HAL_SRAM_Write_32b( &hsram1, &pAddress, pScrBuffer, 0x100);

In a loop but does not produce any Chip Selects or Write pulses.

I have also used *(__IO uint32_t *) 0x60000000 = 0xAAAAAAAA;

In a loop but once again no pulses. I believe that 0x60000000 is the correct address for FMC_NE1 as this is the first Sub Bank of BANK1 of the NOR/PSRAM1 config.

Any help would be grateful.

waclawek.jan · ‎2015-05-24

Posted on May 25, 2015 at 08:39

Post the content of relevant FMC and GPIO registers.

JW

john239955_st · ‎2015-05-26

Posted on May 26, 2015 at 12:21

waclawek.jan · ‎2015-05-26

Posted on May 26, 2015 at 12:54

I mean, content of relevant FMC and GPIO registers as read back (possibly using a debugger or any other means) after the initialization.

JW

john239955_st · ‎2015-05-26

Posted on May 26, 2015 at 13:25

Thanks Jan,

I only have the STM32F427IIT assembled on my board, I'm using an Keil uVision4 and it seems not to like debugging through SW .... maybe I need to upgrade or configure a serial port. I'm not certain that the upper 2 bytes are configured as the Alt Function PortH & I but will check.

Thanks for your help.

John W

john239955_st · ‎2015-05-27

Posted on May 27, 2015 at 20:32

Thanks,

Re:- No 32 bit data bus ... I have the following:-

FMC_BCR1 value of 0x00000a1

MBKEN = 1 Enabled

MWID = 2 32 bits

MTYP = 0 SRAM.

Not sure why 0x...a1 is this because bit10, the reserve bit is high.

Thanks John W

waclawek.jan · ‎2015-05-27

Posted on May 27, 2015 at 22:04

What about this one:

Bit 12 WREN: Write enable bit.

This bit indicates whether write operations are enabled/disabled in the bank by the FMC:

0: Write operations are disabled in the bank by the FMC, an AHB error is reported,

1: Write operations are enabled for the bank by the FMC (default after reset).

Upon attempt to write, the program must have fallen into some of the fault handlers.

The debugging tools are a great help in sorting out these sort of troubles.

JW

john239955_st · ‎2015-05-28

Posted on May 28, 2015 at 10:53

Thanks Jan,

I have updated to Keil uVision5 ... much better.

Does the WREN bit, enable the 'config' of the Bank or allow a write to the external SRAM.

I now get a FMC_NE1 pulse momententarily and it stays low with no further selects, I guess this when an error occurs. Will check.

Thanks John W