Posted on March 17, 2015 at 13:24You'd have to run the processor at a multiple of 50 MHz, ie 150 MHz, and divide down from there. You'd want to check if the PLL generates too much jitter/phase-noise for ethernet applications.
The processor will take an external clock source up to 50 MHz via HSE input.
Also there is the I2SPLL via MCO2
