STM32 SPI/I2S and TI ADS7951 ADC

[electronics]

Posted on July 16, 2012 at 17:09

Hello everybody,

I'm evaluating the STM32F207IG and I need to acquire samples from an ADC from Texas Instruments (ADS7951), which is a 12bit 1MS/s serial ADC.The ADC interface is a sort of SPI, with MISO, clock and a CS line. The CS line should be pulled low to activate the device, should stay low for the whole transfer (>16 clock cycles) and then rise again.The needed waveforms are shown at page 23 of this

http://www.ti.com/lit/gpn/ads7951

.I have to acquire at about 350kS/s with DMA support.I've read the STM32F207IG reference manual, and at page 660/661 of its 

http://www.st.com/internet/com/TECHNICAL_RESOURCES/TECHNICAL_LITERATURE/REFERENCE_MANUAL/CD00225773.pdf

 is described an SPI TI mode that seems similar to the one needed to drive my ADC.Since I'm in the evaluation phase, I do not have devices and boards to hook up an ADC and try, could anyone with hands-on experience with STM32 SPI in TI mode tell me if that interface is compatible with the one needed by that ADC?Regards,Francesco

[waclawek.jan]

Posted on July 17, 2012 at 14:48

From reading the ADS7951 datasheet, it appears that it has a different clock polarity than output by SPI in TI mode, and also it requires more than 16 clocks per sample (the SPI can use only 8 or 16).

JW

[Tesla DeLorean]

Posted on July 17, 2012 at 15:51

 (the SPI can use only 8 or 16).

Or multiples thereof. Suggest you try the part on a breakout board.

[electronics]

Posted on July 17, 2012 at 18:35

The main problem is see is the generation of the CS signal.

From the ADS7951 datasheet, i see that I have to pull the CS signal down, transfer at least 16bits , pull the CS high and clock another few bits before restarting the cycle.Currently I am driving this ADC with a SAM7, using the SSC peripheral which is a lot more configurable configurable than the STM32 one. I use a 20 clock pulse word size, but DMA transfers are only 16 bit wide. The other 4 remaining bits are not used for data transfer, are used only generate the correct CS signal timing.However, talking of STM32, maybe I have an idea. I can program the SPI signals with the correct clock level and polarity, using 8 bit data tranfers. Then I can route the clock signal to a timer input, and use the compare facility to generate an output compare which goes high when the count reaches 16 and goes down again when it reaches 24 (that is a 3 bytes transfer). After this the loop can be started again. This output compare signal can be routed to the ADC CS signal.What do you think? Is it possible to configure the timers in such a way?Regards,Francesco

[emalund]

Posted on July 17, 2012 at 20:59

I have to acquire at about 350kS/s with DMA support.

However, talking of STM32, maybe I have an idea. I can program the SPI signals with the correct clock level and polarity, using 8 bit data tranfers. Then I can route the clock signal to a timer input, and use the compare facility to generate an output compare which goes high when the count reaches 16 and goes down again when it reaches 24 (that is a 3 bytes transfer). After this the loop can be started again. This output compare signal can be routed to the ADC CS signal. worth a try if the DMA is mandatory could you not do it w/o DMA? that seems simpler.  You DO get an interrupt after each byte/word

[waclawek.jan]

Posted on July 18, 2012 at 11:16

>> the SPI can use only 8 or 16

>Or multiples thereof.

But not in TI mode - the CS signal has to be generated regularly, as Francesco wrote, and AFAIK there's no way to suppress it between consecutive transfers. There may be another gotcha, which may not be clear from the ADC datasheet's reading: it may require uninterrupted clock stream to work properly. This sort of ADCs is intended to be used with DSPs, which typically do have the appropriate hardware to run back-to-back conversions continuously. While you could be able to concoct a working setup, you may also consider using a small cheap mcu or CPLD/FPGA as a dedicated interface between the ST32F4xx and the ADC. JW

[electronics]

Posted on July 18, 2012 at 12:55

350kS/s means 350k x3bytes = 1050000 irq per second, that would be a huge amount of CPU load, used only to generate the correct CS timing.

I don't think the CPU would have enough power to handle this. It has to do several other things (communicate over ethernet, drive some motors with PWM, acquire from the internal ADC, etc...).I think DMA is mandatory in such a situation.

[frankmeyer9]

Posted on July 18, 2012 at 15:00

And why don't you use the internal ADC with DMA support ?

The nominal accuracy is the same,and I can't see any other distinct advantage.

[electronics]

Posted on July 18, 2012 at 15:08

Unfortunately the ADC resides on another board which should not be redesigned for backward compatibility reasons.

[frankmeyer9]

Posted on July 18, 2012 at 16:19

Unfortunately the ADC resides on another board which should not be redesigned for backward compatibility reasons.

Reminds me on the infamous A20 gate of the intel x86 family, that was supported up to the Pentium class, just for compatibility with some arcane DOS software. I know neither the project nor that other board. I hope there is something else on it to keep it in, otherwise it's much effort with little output, and most of the controller performance wasted. That might have internal and personal reasons, not the first time I come across that.