SRAM with less adress bits - STM32F407IG

netogodoy · ‎2012-04-18

Posted on April 18, 2012 at 19:25

Hello,

I'm developing a data acquisition system for a Formula SAE team and the electronic module that I'm designing has a FPGA to acquire multiple digital signals in parallel.

The ideia to read the data stored in the FPGA was to make it look like a SRAM memory, it would have the same functionality and some control and adress bits.

I would like to use the FSMC in SRAM mode with 8 or 16 bits of data and only 3 or 4 bits of adress. Also, I would like to use the other adress bits with other peripherals.

The solution that I came up is to only connect the adress pins that I want to use to the FSMC peripheral and leave the other pins unconnected.

For example, only the [3:0] adress pins would be actually used as adress pins. The [25:4] pins would be internally unconnected to FSMC, but connected to other peripheral of my choice.

Am I missing something or there is no problem with this ideia ?

Thanks and sorry for the bad english!

jlchoobs · ‎2012-04-18

Posted on April 19, 2012 at 05:56

Like your idea - good as a class Project - new and creative.

Works like an UART ASIC Chip - simple to use and modular.

And, it leaves the design to use the FPGA for other /and change to other functions too.

You might want to leave a few extra pins as addresses to the FPGA - to allow parallel functionalities on the FPGA - multiple functions from the FPGA via different Addresses.

Or, is this your plan already ?

What FPGA are you using ? If it is Xilinx then you can use the Stm32 to dump the Binary code to the FPGA via I2C, instead of using an additional Seeprom chip.

- How is the weather down there ? - I miss Joinville and Sao Paulo - beautiful places in the world - would like to have a summer house there.

frankmeyer9 · ‎2012-04-19

Posted on April 19, 2012 at 09:48

I did not yet mess a lot with the FSMC, so I'm somehow surprised that it is indeed possible to use just this few address lines. Anyway, the idea behind my suggestion to use a serial protocoll was another one.

As you want to realize a kind of measurement interface with your FPGA, I guess you want to measure thinks which are difficult to achieve with the stm32f4 itself. With just 8 or 16 addresses, it's probably not about the sheer amount of data, but high-resolution timing.

Basically it's about interchanging configuration, command and data items between the uC and your FPGA. If the latter one is autonomous or semiautonomous, you will need to think about synchronization (equivalent to multicore systems). And shared memory is not the best option for that, at least in my experience.

raptorhal2 · ‎2012-04-19

Posted on April 20, 2012 at 02:27

If you wish, send me an e-mail to raptorhal@bellsouth.net describing your design. I would like to have a discussion on your design that has nothing to do with this forum.

Cheers, Hal

alok472 · ‎2012-04-20

Posted on April 21, 2012 at 05:24

What is the speed at which the data acquisition needs to take place from FPGA ? Is it in MHz ? If it is few Khz, then a direct interface to STM32F4 is probably a right choice.

If FPGA is mandatory, follow Clive's suggestion and use Higher order Address bits. If you use lower order bits, the FPGA will be addresssed averytime you access another address from ext memory.