Posted on May 17, 2011 at 13:25I am using SPI2 with DMA4 (rx) and DMA5 (tx). I am trying to do something like the following:
- Transmit using DMA5 with DMA4 disabled. Enable only TCIE on DMA5.
- In DMA5 interrupt handler, configure DMA4 and enable TCIE on it while also reloading DMA5 with enough bytes to generates clocks for the expected number of recevied bytes. I am disabling the DMA5 interrupt at this time.
My expectation is that the received data would be placed in my buffer by DMA4. This is happening, but the buffer is first being padded with 00 values. The number of these values is the same as the number of transmitted bytes from my first step.
I have tried cleaning out the SPI data buffer in my DMA5 isr, and that works if I step through the code, but not when run at full speed. I obviously have a timing problem.
Does anyone know why I am getting data in the rx portion of the SPI data register when the DMA is off? If I step through the code, I can see the data byte transferred as soon as I enable DMA4.
Why does clearing the rx data in the DMA5 handler not fix the problem? I know DMA4 isr has higher priority than DMA5 isr, but since DMA4 isr is not enabled during the first transaction I am confused how this could be happening.
