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simk0024
Associate
April 3, 2016
Question

SPI clock is set different for different audio frequency

  • April 3, 2016
  • 1 reply
  • 677 views
Posted on April 03, 2016 at 05:04

To MCD Application Team and any professional, 

I read through the source code of  \STM32Cube_FW_F4_V1.10.0\Drivers\BSP\STM32F411E-Discovery\stm32f411e_discovery_audio.c

as well as any stm32f4xx_audio.c file.

I notice that in function BSP_AUDIO_OUT_Init(), the I2SCLK is set different for 2 different set of audio frequency, multiple of 8 (8k, 16k, 24k, 32k, etc.) and others (11.025k, 22.050k, 44.1k, etc)

================Source Code============================

 

if((AudioFreq & 0x7) == 0)

  {

    /* Audio frequency multiple of 8 (8/16/32/48/96/192)*/

    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN = 192 Mhz */

    /* I2SCLK = PLLI2S_VCO Output/PLLI2SR = 192/6 = 32 Mhz */

    rccclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;

    rccclkinit.PLLI2S.PLLI2SN = 192;

    rccclkinit.PLLI2S.PLLI2SR = 6;

    HAL_RCCEx_PeriphCLKConfig(&rccclkinit);

  }

 

else

  {

    /* Other Frequency (11.025/22.500/44.100) */

    /* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN = 290 Mhz */

    /* I2SCLK = PLLI2S_VCO Output/PLLI2SR = 290/2 = 145 Mhz */

    rccclkinit.PeriphClockSelection = RCC_PERIPHCLK_I2S;

    rccclkinit.PLLI2S.PLLI2SN = 290;

    rccclkinit.PLLI2S.PLLI2SR = 2;

    HAL_RCCEx_PeriphCLKConfig(&rccclkinit);

  }

================END=====================================

What is the purpose for this setting??

Thank you
    This topic has been closed for replies.

    1 reply

    Tesla DeLorean
    Guru
    April 3, 2016
    Posted on April 03, 2016 at 14:38

    What is the purpose for this setting??

    Presumably to allow you to hit the specific rates via the integer dividers used elsewhere?

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