2013-05-22 08:23 AM
Hello,
I'm working on an interface based on STM32F407 with 48 buttons. I use 74HC165 shift registers parrallel in/serial out to multiplex my buttons states.I need to cascading 6 registers to connect the 48 buttons.This is my question: is it preferable to cascading the 6 registers or to ''ungroup'' them and cascading them 3 by 3 ? I mean, 3 registers are chained and communicate with the microcontroller, and 3 others registers are chained and communicate with the microcontroller with another pins.What is the best way to optimize the communication speed ?2013-05-22 08:29 AM
If you used GPIO you could read multiple chains, and use a single clock.
Using SPI would require less software overhead, and could be clocked quickly.2013-05-22 08:40 AM
Hello clive1,
I use GPIOs to read my registers.So you advise me to unchain my registers ? And use a single clock for all of them...2013-05-22 08:57 AM
Parallel
It's really up to you, the GPIO port can read 16-bit wide banks. Use more scan chains to decimate the read time. So 1x48 2x24 3x16 6x8 Decide how many pins you want to commit to the interface.2013-05-22 10:24 AM
Whatever I choose 1x48, 2x24, 3x16 of 6x8, it will be no effect on speed ? The fact is i'm afraid that reading 48 inputs continiusly to scan every buttons will take a lot of STM32 ressources...
2013-05-22 11:26 AM
Why do you need to scan it continuously, are those some special high-speed keys or is it just a regular keyboard?
With normal keyboard it would be enough to scan it 100 times per second, takes less than one percent of CPU power and no shift register is really necessary as 6x8 matrix only needs 14 i/o lines.2013-05-22 12:00 PM
Whatever I choose 1x48, 2x24, 3x16 of 6x8, it will be no effect on speed ?
Ok, let's reiterate. You can read 16 GPIO pins from a single bank via GPIOx->IDR By using multiple pins, connected to different scan chains (your end-to-end connected shift registers), you
http://dictionary.reference.com/browse/decimate?s=t
the work load. ie you send one clock pulse, you can read 3 different chains, clock it 16 times, and you're read all bits from all chains.2013-05-22 03:38 PM
Kill those six shift-registers!
Combining advice of both Clive and Knik - we've found it useful to employ the 6x8 matrix scheme - but impose a 74hct30 (8 input nand gate) between your 8 switch inputs and one added GPIO. This extra chip justifies its use by causing an interrupt (fed to that extra GPIO) upon keypress - greatly reducing the load upon the MCU. And eliminates all of those shift registers - causing speed-up and reducing size/cost... Upon that keypress interrupt - MCU outputs single, ''walking'' low to your matrix - which thus identifies the active key. Trick is to ''latch'' all 6 outputs to matrix - low initially - so that any keypress will be seen by the nand gate - which triggers your keypress interrupt. Beauty of this method is that zero burden is imposed upon the MCU when keys are inactive. Your proposed parallel to serial scheme - in contrast - demands constant clocking - and reads - to detect keypress - even when the keys have long been inactive... Method I propose commands the MCU's attention only when - and if needed - and does so efficiently... In this manner up to 64 keys may be quickly/easily scanned/read - at the cost of 17 GPIO (8 out, 8 in, 1 interrupt) & the addition of one low-cost IC. (if the IC is unwanted - a diode array can achieve similar - but at reduced noise margin)2013-05-23 03:14 AM
Thanks jj, clive & Knick!
Knick, it's a regular keyboard.I don't know anything about 6x8 matrix... do you have documentation about this ? I found nothing... The solution with the matrix + the 75HCT30 seems interesting !Clive, I understand your solution, this answers my question perfectly ! So GPIOs can read data in parrallel.2013-05-23 06:30 AM
Google ''keyboard matrix'' and you will get nice links.
It's nothing special just a standard keyboard.