Hello everyone,
I need to build a system to test a bunch of existing memory modules built around 512 Mbit SDRAM chips (4 chips each for total of 256 MBytes).
The attached schematic shows the original design of the memory module and how it's connected to the MPU of target system. Apparently the MPU used has 30-bit address lines and 32-bit wide data bus. I believe that's why they only exposed two CS signals on the edge connector.
On the STM32F429, there are two SDRAM banks, two unique NEs and CKEs for two SDRAM devices. However, for the purpose of testing the entire memory on the module, I need to be able to perform read/write tests on all chips, that is four for this module.
The question is, what would be the best approach to do it when only two CS signals are exposed on the edge connector of the module? Of course, on the STM32F429 based board, address, data bus, CAS, RAS, WE, CLK, BA0/1, DQMU/L signals are going to be shared.
With two CS signals used for all 4 chips, the only feasible scenario I have in mind is to use two buffers to switch address signals between upper and lower chips, and another two 16-bit transceivers to switch data bus signals between upper and lower chips. I was wondering if there's any better way to do it. The only unique signals for each chip (on the original design of module) are the DQMU/L signals. Could it be possible to use those to enable/disable a chip at a time?
