2014-02-25 01:22 AM
Hi,
I am having troubles with the subsecond register on stm32 I have a datalogger which logs data with a timestamp. I am doing multiple logs (~30) per second, so wanted to log sub-seconds as well. HOWEVER, as soon as I read the sub-second register (RTC_SSR), the seconds no longer increment properly and skip seconds! I have not enabled the SSR register or anything, do I need to? I just store the register as an unsigned int, and use the formula frac = (float)(PREDIV_S - fracsec) / (float)(PREDIV_S + 1); to get the subsecond as a fraction of a second. Without reading the register, the timer increments the seconds correctly, and I make about 30 logs per second. i.e about 30 logs with timestamps 12:00:01, and then 30 logs at timestamp 12:00:02 However, as soon as I read the SSR register, things start playing up. The log will increment the subsecond 12:00:01.01 -> 12:00:01.99, and then sub-seconds will start again but RTC_TR will remain at 1second (i.e 12:00:01.01 -> 12:00:01.99 again), and the SSR register will keep ticking over multiple times before RTC_TR will change. Then, all of a sudden, the RTC_TR seconds will jump ahead 3-4+ seconds and the logging will read 12:00:05.01 -> 12:00:05.99 over and over. Hope you can understand this explanation! Why wont the seconds increment correctly when reading the SSR register? Just commenting out the read from the SSR register will allow the seconds to perform as normal again - all other code is identical.... I see in the note section of the STM reference manual it states:''Note: SS can be larger than PREDIV_S only after a shift operation. In that case, the correcttime/date is one second less than as indicated by RTC_TR/RTC_DR.'' However, I'm seeing a 3+ second skip in the TR register, so this cant be the cause. AND it seems to be random. I have the time output to a clock on a LCD and the minutes seem to match up with my clock. i.e 1 minute reading on the RTC = 60seconds in real life. Synch and asynch prescalers are as default. Any thoughts?? #rtc #ssr #stm32
2014-02-25 01:42 AM
Sounds to me like the effects if you are reading the ''shadow'' registers but fail to read RTC_DR every time.
Read up on the BYPSHAD control bit in RTC_CR (reference manual 26.3.6 of Rev 5 for the stm32f4xx).> To ensure consistency between the 3 values, reading either RTC_SSR or> RTC_TR locks the values in the higher-order calendar shadow registers> until RTC_DR is read. Me? I tend to set BYPSHAD and re-read until I get a coherent set. - Danish2014-02-26 02:06 AM
You sir, are a legend! Thank-you so much
I was reading TR, DR, and then SSR. ''In case the software makes read accesses to the calendar in a time interval smaller than 2 RTCCLK periods: RSF must be cleared by software after the first calendar read, and then the software must wait until RSF is set before reading again the RTC_SSR, RTC_TR and RTC_DR registers.'' RSF was getting cleared after reading TR & DR, but then a new read (SRR) within the 2 clock cycles locked it again - and I wasn't resetting manually. Changing the order of the read fixed the problem! Cheers!2017-08-06 10:54 AM
Hi
I am reading the rtc with BYPSHAD cleared . I wait till the RSF flag is set, then readin the registers, and works okay. I couldnt find anywhere if I have to clear the RSF flag with the command RTC->ISR &=~RTC_ISR_RSF; or if the flag automatically gets cleared. Can anyone let me know if I clear it manually ?
Thanks
Scott