RTC external quartz drive level impact

[I2.1]

Hi,

I have questions about drive level impact on RTC configuration.

I'm using a STM32U575, with a 32kHz quartz as LSE for my RTC.

Transconductance of my quartz is 1,5µA/V, and drive level is 1.0µW max.

I'm using medium high for my drive level, according to the datasheet, Gmcrit and LSE current consumption should be ok.

I've seen in the AN2867 several other quartz with the same characteristics in the Recommanded crystal table.

But, when I'm probing my quartz signal, I'm not meeting the 0.3V peak to peak.

 

I tried with the other drive levels, but I'm getting the same peak to peak value, around 240mV.

Can you please help me understand ?

[AScha.3 · Accepted solution]

the signal here is high impedance, so you cannot use a standard probe and see at DSO "full" signal.

(need active FET probe, if you really insist on probing here).

in my tests high or medium high drive giving clean working rcc clock.

lower drive gives problems on many boards, some dont start at all.

a little bit dirt or remains from solder flux is enough to stop clock then.

so, if running fine with using medium high drive level - good.

[I2.1]

Ok thank, rtc is running indeed.