RM0394 SRAM2 connectivity in bus matrix

waclawek.jan · ‎2025-12-05

In the lower-end STM32L4, covered by RM0394, SRAM is partitioned into two parts, SRAM1 and SRAM2.

SRAM2 (besides being "special" in that it has ECC and automatic erase facities), is mapped at both 0x1000'0000 and at the end of SRAM1 in the 0x200x'xxxx area.

In Figure 1 System architecture, SRAM2 does not have the connection needed for that second mapping, i.e. to the S-bus of the processor.

JW

mƎALLEm · ‎2025-12-10

Hello @waclawek.jan ,

According to the internal team it's indeed a missing connection.

Hope this will be fixed in the coming revisions of the document.

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mƎALLEm · ‎2025-12-05

Hello,

I will raise that question to the internal team for review and for an eventual fix (if relevant). Internal ticket number 223306.

Knowing that in the paragraph: 2.1.3 S2: S-bus: no mention of SRAM2.

Thank you for your contribution.

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mƎALLEm · ‎2025-12-10

Hello @waclawek.jan ,

According to the internal team it's indeed a missing connection.

Hope this will be fixed in the coming revisions of the document.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.

mƎALLEm · ‎2025-12-16

This thread will be closed as the fix is confirmed internally and it will be available in the next coming revisions of the document.

To give better visibility on the answered topics, please click on "Accept as Solution" on the reply which solved your issue or answered your question.