I'm trying to implement a serial bit-stream input (PCM-style) on an STM32U575. I have set up an EXTI channel to capture the incoming clock signal and then I'm using the following code in the ISR to capture the data bits:
__attribute__ ((section(".RamFunc"))) void EXTI7_IRQHandler(void) {
SPLITTER_CLK_OUT_GPIO_Port->ODR |= SPLITTER_CLK_OUT_Pin;
if(haveFS == 0) {
// CLK pulse whilst in idle state - is there a FS?
if(PCM_FS_IN_GPIO_Port->IDR & PCM_FS_IN_Pin) {
haveFS = 1;
slotCount = 0;
bitsCount = bits_per_slot;
pDataSlot = pData;
} else {
return;
}
}
// Read next data bit
if(PCM_DATA_IN_GPIO_Port->IDR & PCM_DATA_IN_Pin) {
*pDataSlot |= (1 << --bitsCount); // Set bit
} else {
*pDataSlot &= ~(1 << --bitsCount); // Clear bit
}
if(_internal.bitsCount == 0) {
// Received one slot
slotCount++;
pDataSlot++;
bitsCount = bits_per_slot;
}
// Have we received all slots?
if(_internal.slotCount == _internal.total_slots) {
// Signal done somehow?
slotCount = 0;
haveFS = 0; // Now we need to expect another FS pulse...
}
__HAL_GPIO_EXTI_CLEAR_RISING_IT(PCM_CLK_IN_Pin);
SPLITTER_CLK_OUT_GPIO_Port->ODR &= ~SPLITTER_CLK_OUT_Pin;
}
This works for incoming clock frequencies up to approx 2MHz, but I really need to be able to handle about 4MHz. I've got the main clock configured at 160MHz.
I think my immediate issue is the interrupt latency, using the pin toggles in the ISR I can measure ~250ns latency, even after attempting to run the ISR from RAM. I'm not overly familiar with the architecture of the M33 core etc. - hoping someone might be able to give me some suggestions on how to improve this further!
TIA
