RCC_CR_PLLSAI2RDY is not set when initializing PLLSAI2

[Johnny8923]

Hello,

I'm using a STM32L476 and the HAL from ST tag: v1.12.0 and it appears in some cases that when I'm configuring the PLL for the SAI2 peripheral that the RCC_CR_PLLSAI2RDY flag from the RCC->CR register is not ready.

Did anyone had the same issue? What could cause this?

Thanks and advance and best regards,

Jonathan

[waclawek.jan]

> in some cases

Elaborate.

What's the primary clock source? Is it stable at that point? How is the SAI2 PLL set up? Read out and check/post content of relevant RCC registers when the timeout occurs.

JW

[Johnny8923]

Thanks for your answer, the primary clock source is HSE (16MHz), here's my configuration:

    PeriphClkInit.PLLSAI2.PLLSAI2Source = RCC_PLLSOURCE_HSE;

    PeriphClkInit.PLLSAI2.PLLSAI2M = 1;

    PeriphClkInit.PLLSAI2.PLLSAI2N = 16;

    PeriphClkInit.PLLSAI2.PLLSAI2P = RCC_PLLP_DIV7;

    PeriphClkInit.PLLSAI2.PLLSAI2R = RCC_PLLR_DIV2;

    PeriphClkInit.PLLSAI2.PLLSAI2ClockOut = RCC_PLLSAI2_SAI2CLK;

I'll check the state of the RCC registers when the timeout occurs and put the results here.

Jonathan

[waclawek.jan]

> PeriphClkInit.PLLSAI2.PLLSAI2M = 1;

In the 'L476, there is only one single M prescaler shared by all the PLLs. I don't know how is this handled by Cube/HAL - I don't use it - but IMO you have to make sure it's set to the same value for all PLL setup functions.

16MHz input frequency is at the upper end of the PLL's input range, maybe you want to use a divider to make sure the input clock duty is withing the specified 45-55%.

Also make sure that the VCO output frequency is adequate for the selected VSO, see PLL, PLLSAI1, PLLSAI2 characteristics  table in datasheet.

JW