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"OTP" memory comments and request

gahelton1
Associate III

I have a project (joystick controller) that requires a small amount of non-volatile memory (10 to 16 bytes) for calibration data. Presently, I am using a STM32F4 series micro for this project. Although it's a bit overkill, my initial plan was to use a sector of flash to store the calibration data, but it turns out that the sector size on the part I'm using is 16K !  That's a pretty big waste of flash for a few bytes of non-volatile storage. So, I took a look at OTP. While OTP would potentially work without wasting lots of memory, by definition, it's One Time Programmable. I anticipate that the joystick may need to be re-calibrated occasionally, so the present way OTP is implemented is not very useful without jumping through some hoops.

So here is what would be nice.

A user flash area (512 bytes would be just fine for most applications) that was divided into blocks just as the existing OTP memory is. The difference would be that until the lock bit(s) were set on a block, the memory would remain programmable and erasable. However, once a lock bit is set on the block, that block would become permanently locked, and could not be erased (not even with mass erase operation). This could be implemented by making the lock bits non-erasable. Once locked, that's it !  In my opinion, this would be the best of all worlds. Non-volatile user flash area when you need it, OTP when you need it. Of course, you could have both by only locking the blocks that need to be OTP (areas like serial numbers, etc).

Of course, one could always add an external EEPROM, but my request seems like a relatively simple thing to implement for those who don't need a large amount of NVM.

Everyone please comment. Maybe we can get this a feature on future versions.

 

Thanks,

Greg

 

10 REPLIES 10
Nikita91
Lead II

I already asked for EEPROM at the C0 webinar.

They say the C0 in intended to replace 8 bitters. But it lacks EEPROM which is present in most 8 bits!

Perhaps they want to sell their EEPROM chips, a marketing constraint?